/* SPDX-License-Identifier: Apache-2.0 */

#ifndef __SUN20IW5_REG_CCU_H__
#define __SUN20IW5_REG_CCU_H__

#include <reg-ncat.h>

/* CCU AON */
#define PLL_CPU_CTRL_REG 0x00000000//PLL_CPU Control Register
#define PLL_CPU_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_CPU_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
#define PLL_CPU_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_CPU_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_CPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
#define PLL_CPU_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_CPU_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_CPU_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_CPU_CTRL_REG_LOCK_OFFSET 28
#define PLL_CPU_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
#define PLL_CPU_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_CPU_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_CPU_CTRL_REG_PLL_LOCK_TIME_OFFSET 24
#define PLL_CPU_CTRL_REG_PLL_LOCK_TIME_CLEAR_MASK (0x07000000)
#define PLL_CPU_CTRL_REG_PLL_N_OFFSET 8
#define PLL_CPU_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_CPU_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_CPU_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_CPU_CTRL_REG_PLL_INPUT_DIV_OFFSET 2
#define PLL_CPU_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x0000000c)
#define PLL_CPU_CTRL_REG_PLL_INPUT_DIV_1 0b00
#define PLL_CPU_CTRL_REG_PLL_INPUT_DIV_2 0b01
#define PLL_CPU_CTRL_REG_PLL_INPUT_DIV_4 0b10
#define PLL_CPU_CTRL_REG_PLL_M_OFFSET 0
#define PLL_CPU_CTRL_REG_PLL_M_CLEAR_MASK (0x00000003)

#define PLL_PERI_CTRL0_REG 0x00000020//PLL_PERI Control0 Register
#define PLL_PERI_CTRL0_REG_PLL_EN_OFFSET 31
#define PLL_PERI_CTRL0_REG_PLL_EN_CLEAR_MASK (0x80000000)
#define PLL_PERI_CTRL0_REG_PLL_EN_DISABLE 0b0
#define PLL_PERI_CTRL0_REG_PLL_EN_ENABLE 0b1
#define PLL_PERI_CTRL0_REG_PLL_LDO_EN_OFFSET 30
#define PLL_PERI_CTRL0_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
#define PLL_PERI_CTRL0_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_PERI_CTRL0_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_PERI_CTRL0_REG_LOCK_ENABLE_OFFSET 29
#define PLL_PERI_CTRL0_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
#define PLL_PERI_CTRL0_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_PERI_CTRL0_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_PERI_CTRL0_REG_LOCK_OFFSET 28
#define PLL_PERI_CTRL0_REG_LOCK_CLEAR_MASK (0x10000000)
#define PLL_PERI_CTRL0_REG_LOCK_UNLOCKED 0b0
#define PLL_PERI_CTRL0_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_PERI_CTRL0_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_PERI_CTRL0_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
#define PLL_PERI_CTRL0_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_PERI_CTRL0_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_PERI_CTRL0_REG_PLL_SDM_EN_OFFSET 24
#define PLL_PERI_CTRL0_REG_PLL_SDM_EN_CLEAR_MASK (0x01000000)
#define PLL_PERI_CTRL0_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_PERI_CTRL0_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_PERI_CTRL0_REG_PLL_N_OFFSET 8
#define PLL_PERI_CTRL0_REG_PLL_N_CLEAR_MASK (0x0000ff00)
#define PLL_PERI_CTRL0_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_PERI_CTRL0_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
#define PLL_PERI_CTRL0_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_PERI_CTRL0_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_PERI_CTRL0_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_PERI_CTRL0_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_PERI_CTRL0_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
#define PLL_PERI_CTRL0_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_PERI_CTRL0_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_PERI_CTRL0_REG_PLL_P2_OFFSET 3
#define PLL_PERI_CTRL0_REG_PLL_P2_CLEAR_MASK (0x00000018)
#define PLL_PERI_CTRL0_REG_PLL_INPUT_DIV_OFFSET 0
#define PLL_PERI_CTRL0_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000007)
#define PLL_PERI_CTRL0_REG_PLL_INPUT_DIV_DIV1 0b000
#define PLL_PERI_CTRL0_REG_PLL_INPUT_DIV_DIV2 0b001
#define PLL_PERI_CTRL0_REG_PLL_INPUT_DIV_DIV3 0b010
#define PLL_PERI_CTRL0_REG_PLL_INPUT_DIV_DIV4 0b011
#define PLL_PERI_CTRL0_REG_PLL_INPUT_DIV_DIV5 0b100

#define PLL_PERI_CTRL1_REG 0x00000024//PLL_PERI Control1 Register
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_12_EN_OFFSET 15
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_12_EN_CLEAR_MASK (0x00008000)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_12_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_12_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_24_EN_OFFSET 14
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_24_EN_CLEAR_MASK (0x00004000)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_24_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_24_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_48_EN_OFFSET 13
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_48_EN_CLEAR_MASK (0x00002000)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_48_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_48_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_96_EN_OFFSET 12
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_96_EN_CLEAR_MASK (0x00001000)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_96_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_96_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_118_EN_OFFSET 11
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_118_EN_CLEAR_MASK (0x00000800)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_118_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_118_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_192_EN_OFFSET 10
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_192_EN_CLEAR_MASK (0x00000400)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_192_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_192_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_219_EN_OFFSET 9
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_219_EN_CLEAR_MASK (0x00000200)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_219_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_219_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_236_EN_OFFSET 8
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_236_EN_CLEAR_MASK (0x00000100)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_236_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_236_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_307_EN_OFFSET 7
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_307_EN_CLEAR_MASK (0x00000080)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_307_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_307_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_341_EN_OFFSET 6
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_341_EN_CLEAR_MASK (0x00000040)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_341_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_341_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_384_EN_OFFSET 5
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_384_EN_CLEAR_MASK (0x00000020)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_384_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_384_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_512_EN_OFFSET 4
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_512_EN_CLEAR_MASK (0x00000010)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_512_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_512_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_614_EN_OFFSET 3
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_614_EN_CLEAR_MASK (0x00000008)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_614_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_614_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_768_EN_OFFSET 2
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_768_EN_CLEAR_MASK (0x00000004)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_768_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_768_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_1024_EN_OFFSET 1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_1024_EN_CLEAR_MASK (0x00000002)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_1024_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_1024_EN_ENABLE 0b1
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_1536_EN_OFFSET 0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_1536_EN_CLEAR_MASK (0x00000001)
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_1536_EN_DISABLE 0b0
#define PLL_PERI_CTRL1_REG_PLL_PERI_CKO_1536_EN_ENABLE 0b1

#define PLL_VIDEO_CTRL_REG 0x00000040//PLL_VIDEO Control Register
#define PLL_VIDEO_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_VIDEO_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
#define PLL_VIDEO_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_VIDEO_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_VIDEO_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_VIDEO_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_VIDEO_CTRL_REG_LOCK_OFFSET 28
#define PLL_VIDEO_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
#define PLL_VIDEO_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_VIDEO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x01000000)
#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_VIDEO_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_VIDEO_CTRL_REG_PLL_N_OFFSET 8
#define PLL_VIDEO_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_VIDEO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_VIDEO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_VIDEO_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
#define PLL_VIDEO_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000006)
#define PLL_VIDEO_CTRL_REG_PLL_INPUT_DIV_1 0b00
#define PLL_VIDEO_CTRL_REG_PLL_INPUT_DIV_2 0b01
#define PLL_VIDEO_CTRL_REG_PLL_INPUT_DIV_4 0b10
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_VIDEO_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK (0x00000001)

#define PLL_CSI_CTRL_REG 0x00000048//PLL_CSI Control Register
#define PLL_CSI_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_CSI_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
#define PLL_CSI_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_CSI_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_CSI_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_CSI_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
#define PLL_CSI_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_CSI_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_CSI_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_CSI_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
#define PLL_CSI_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_CSI_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_CSI_CTRL_REG_LOCK_OFFSET 28
#define PLL_CSI_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
#define PLL_CSI_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_CSI_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_CSI_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_CSI_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x01000000)
#define PLL_CSI_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_CSI_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_CSI_CTRL_REG_PLL_FACTOR_N_OFFSET 8
#define PLL_CSI_CTRL_REG_PLL_FACTOR_N_CLEAR_MASK (0x0000ff00)
#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_CSI_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_CSI_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_CSI_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
#define PLL_CSI_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000006)
#define PLL_CSI_CTRL_REG_PLL_INPUT_DIV_1 0b00
#define PLL_CSI_CTRL_REG_PLL_INPUT_DIV_2 0b01
#define PLL_CSI_CTRL_REG_PLL_INPUT_DIV_4 0b10
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_CSI_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK (0x00000001)

#define PLL_AUDIO_CTRL_REG 0x00000078//PLL_AUDIO Control Register
#define PLL_AUDIO_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_AUDIO_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
#define PLL_AUDIO_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_AUDIO_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_AUDIO_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_AUDIO_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_AUDIO_CTRL_REG_LOCK_OFFSET 28
#define PLL_AUDIO_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
#define PLL_AUDIO_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_AUDIO_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_AUDIO_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x01000000)
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_AUDIO_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_AUDIO_CTRL_REG_PLL_P1_OFFSET 20
#define PLL_AUDIO_CTRL_REG_PLL_P1_CLEAR_MASK (0x00700000)
#define PLL_AUDIO_CTRL_REG_PLL_P0_OFFSET 16
#define PLL_AUDIO_CTRL_REG_PLL_P0_CLEAR_MASK (0x00070000)
#define PLL_AUDIO_CTRL_REG_PLL_FACTOR_N_OFFSET 8
#define PLL_AUDIO_CTRL_REG_PLL_FACTOR_N_CLEAR_MASK (0x0000ff00)
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_AUDIO_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_AUDIO_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000006)
#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV_1 0b00
#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV_2 0b01
#define PLL_AUDIO_CTRL_REG_PLL_INPUT_DIV_4 0b10

#define PLL_DDR_CTRL_REG 0x00000080//PLL_DDR Control Register
#define PLL_DDR_CTRL_REG_PLL_EN_OFFSET 31
#define PLL_DDR_CTRL_REG_PLL_EN_CLEAR_MASK (0x80000000)
#define PLL_DDR_CTRL_REG_PLL_EN_DISABLE 0b0
#define PLL_DDR_CTRL_REG_PLL_EN_ENABLE 0b1
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_OFFSET 30
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_CLEAR_MASK (0x40000000)
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_DISABLE 0b0
#define PLL_DDR_CTRL_REG_PLL_LDO_EN_ENABLE 0b1
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_OFFSET 29
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_CLEAR_MASK (0x20000000)
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_DISABLE 0b0
#define PLL_DDR_CTRL_REG_LOCK_ENABLE_ENABLE 0b1
#define PLL_DDR_CTRL_REG_LOCK_OFFSET 28
#define PLL_DDR_CTRL_REG_LOCK_CLEAR_MASK (0x10000000)
#define PLL_DDR_CTRL_REG_LOCK_UNLOCKED 0b0
#define PLL_DDR_CTRL_REG_LOCK_LOCKED__IT_INDICATES_THAT_THE_PLL_HAS_BEEN_STABLE 0b1
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_OFFSET 27
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK (0x08000000)
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_DISABLE 0b0
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_GATE_ENABLE 0b1
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_OFFSET 24
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_CLEAR_MASK (0x01000000)
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_DISABLE 0b0
#define PLL_DDR_CTRL_REG_PLL_SDM_EN_ENABLE 0b1
#define PLL_DDR_CTRL_REG_PLL_N_OFFSET 8
#define PLL_DDR_CTRL_REG_PLL_N_CLEAR_MASK (0x0000ff00)
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_OFFSET 6
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_CLEAR_MASK (0x000000c0)
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_21_29_CLOCK_CYCLES 0b00
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_22_28_CLOCK_CYCLES 0b01
#define PLL_DDR_CTRL_REG_PLL_UNLOCK_MDSEL_20_30_CLOCK_CYCLES 0b10
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_OFFSET 5
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_CLEAR_MASK (0x00000020)
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_24_26_CLOCK_CYCLES 0b0
#define PLL_DDR_CTRL_REG_PLL_LOCK_MDSEL_23_27_CLOCK_CYCLES 0b1
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_OFFSET 1
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK (0x00000006)
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_1 0b00
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_2 0b01
#define PLL_DDR_CTRL_REG_PLL_INPUT_DIV_4 0b10
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_OFFSET 0
#define PLL_DDR_CTRL_REG_PLL_OUTPUT_DIV2_CLEAR_MASK (0x00000001)

#define PLL_PERI_PAT0_CTRL_REG 0x00000120//PLL_PERI Pattern0 Control Register
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 30
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0xc0000000)
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0b00
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0b01
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b10
#define PLL_PERI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0b11
#define PLL_PERI_PAT0_CTRL_REG_WAVE_STEP_OFFSET 21
#define PLL_PERI_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x3fe00000)
#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK (0x00180000)
#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_40MHZ 0b00
#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_20MHZ 0b01
#define PLL_PERI_PAT0_CTRL_REG_SDM_CLK_SEL_10MHZ 0b10
#define PLL_PERI_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_PERI_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
#define PLL_PERI_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_PERI_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_PERI_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_PERI_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_PERI_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_PERI_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_PERI_PAT1_CTRL_REG 0x00000124//PLL_PERI Pattern1 Control Register
#define PLL_PERI_PAT1_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_PERI_PAT1_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
#define PLL_PERI_PAT1_CTRL_REG_SDM_CLK_SEL_OFFSET 25
#define PLL_PERI_PAT1_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK (0x0e000000)
#define PLL_PERI_PAT1_CTRL_REG_SDM_CLK_SEL_40MHZ 0b000
#define PLL_PERI_PAT1_CTRL_REG_SDM_CLK_SEL_20MHZ 0b001
#define PLL_PERI_PAT1_CTRL_REG_SDM_CLK_SEL_13MHZ 0b010
#define PLL_PERI_PAT1_CTRL_REG_SDM_CLK_SEL_10MHZ 0b011
#define PLL_PERI_PAT1_CTRL_REG_SDM_CLK_SEL_8MHZ 0b100
#define PLL_PERI_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_PERI_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
#define PLL_PERI_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_PERI_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
#define PLL_PERI_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_PERI_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_VIDEO_PAT0_CTRL_REG 0x00000140//PLL_VIDEO Pattern0 Control Register
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 30
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0xc0000000)
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0b00
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0b01
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b10
#define PLL_VIDEO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0b11
#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_STEP_OFFSET 21
#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x3fe00000)
#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK (0x00180000)
#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_40MHZ 0b00
#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_20MHZ 0b01
#define PLL_VIDEO_PAT0_CTRL_REG_SDM_CLK_SEL_10MHZ 0b10
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_VIDEO_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_VIDEO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_VIDEO_PAT1_CTRL_REG 0x00000144//PLL_VIDEO Pattern1 Control Register
#define PLL_VIDEO_PAT1_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_VIDEO_PAT1_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
#define PLL_VIDEO_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_VIDEO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_VIDEO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_CSI_PAT0_CTRL_REG 0x00000148//PLL_CSI Pattern0 Control Register
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 30
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0xc0000000)
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0b00
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0b01
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b10
#define PLL_CSI_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0b11
#define PLL_CSI_PAT0_CTRL_REG_WAVE_STEP_OFFSET 21
#define PLL_CSI_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x3fe00000)
#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK (0x00180000)
#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_40MHZ 0b00
#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_20MHZ 0b01
#define PLL_CSI_PAT0_CTRL_REG_SDM_CLK_SEL_10MHZ 0b10
#define PLL_CSI_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_CSI_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
#define PLL_CSI_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_CSI_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_CSI_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_CSI_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_CSI_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_CSI_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_CSI_PAT1_CTRL_REG 0x0000014c//PLL_CSI Pattern1 Control Register
#define PLL_CSI_PAT1_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_CSI_PAT1_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
#define PLL_CSI_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_CSI_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
#define PLL_CSI_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_CSI_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
#define PLL_CSI_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_CSI_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_AUDIO_PAT0_CTRL_REG 0x00000178//PLL_AUDIO Pattern0 Control Register
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 30
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0xc0000000)
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0b00
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0b01
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b10
#define PLL_AUDIO_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0b11
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_OFFSET 21
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x3fe00000)
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK (0x00180000)
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_40MHZ 0b00
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_20MHZ 0b01
#define PLL_AUDIO_PAT0_CTRL_REG_SDM_CLK_SEL_10MHZ 0b10
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_AUDIO_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_AUDIO_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_AUDIO_PAT1_CTRL_REG 0x0000017c//PLL_AUDIO Pattern1 Control Register
#define PLL_AUDIO_PAT1_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_AUDIO_PAT1_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_AUDIO_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_AUDIO_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_DDR_PAT0_CTRL_REG 0x00000180//PLL_DDR Pattern0 Control Register
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_OFFSET 30
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_CLEAR_MASK (0xc0000000)
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_0 0b00
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_DC_1 0b01
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_1BIT 0b10
#define PLL_DDR_PAT0_CTRL_REG_SPR_FREQ_MODE_TRIANGULAR_NBIT 0b11
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_OFFSET 21
#define PLL_DDR_PAT0_CTRL_REG_WAVE_STEP_CLEAR_MASK (0x3fe00000)
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_OFFSET 19
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_CLEAR_MASK (0x00180000)
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_40MHZ 0b00
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_20MHZ 0b01
#define PLL_DDR_PAT0_CTRL_REG_SDM_CLK_SEL_10MHZ 0b10
#define PLL_DDR_PAT0_CTRL_REG_FREQ_OFFSET 17
#define PLL_DDR_PAT0_CTRL_REG_FREQ_CLEAR_MASK (0x00060000)
#define PLL_DDR_PAT0_CTRL_REG_FREQ_31_5KHZ 0b00
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32KHZ 0b01
#define PLL_DDR_PAT0_CTRL_REG_FREQ_32_5KHZ 0b10
#define PLL_DDR_PAT0_CTRL_REG_FREQ_33KHZ 0b11
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_OFFSET 0
#define PLL_DDR_PAT0_CTRL_REG_WAVE_BOT_CLEAR_MASK (0x0001ffff)

#define PLL_DDR_PAT1_CTRL_REG 0x00000184//PLL_DDR Pattern1 Control Register
#define PLL_DDR_PAT1_CTRL_REG_SIG_DELT_PAT_EN_OFFSET 31
#define PLL_DDR_PAT1_CTRL_REG_SIG_DELT_PAT_EN_CLEAR_MASK (0x80000000)
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_OFFSET 24
#define PLL_DDR_PAT1_CTRL_REG_DITHER_EN_CLEAR_MASK (0x01000000)
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_OFFSET 20
#define PLL_DDR_PAT1_CTRL_REG_FRAC_EN_CLEAR_MASK (0x00100000)
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_OFFSET 0
#define PLL_DDR_PAT1_CTRL_REG_FRAC_IN_CLEAR_MASK (0x0001ffff)

#define PLL_CPU_BIAS_REG 0x00000300//PLL_CPU Bias Register
#define PLL_CPU_BIAS_REG_PLL_VCO_RST_IN_OFFSET 31
#define PLL_CPU_BIAS_REG_PLL_VCO_RST_IN_CLEAR_MASK (0x80000000)
#define PLL_CPU_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_CPU_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_PERI_BIAS_REG 0x00000320//PLL_PERI Bias Register
#define PLL_PERI_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_PERI_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_VIDEO_BIAS_REG 0x00000340//PLL_VIDEO Bias Register
#define PLL_VIDEO_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_VIDEO_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_CSI_BIAS_REG 0x00000348//PLL_CSI Bias Register
#define PLL_CSI_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_CSI_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_AUDIO_BIAS_REG 0x00000378//PLL_AUDIO Bias Register
#define PLL_AUDIO_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_AUDIO_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_DDR_BIAS_REG 0x00000380//PLL_DDR Bias Register
#define PLL_DDR_BIAS_REG_PLL_CP_OFFSET 16
#define PLL_DDR_BIAS_REG_PLL_CP_CLEAR_MASK (0x001f0000)

#define PLL_CPU_TUN_REG 0x00000400//PLL_CPU Tuning Register
#define PLL_CPU_TUN_REG_PLL_VCO_OFFSET 28
#define PLL_CPU_TUN_REG_PLL_VCO_CLEAR_MASK (0x70000000)
#define PLL_CPU_TUN_REG_PLL_VCO_GAIN_OFFSET 24
#define PLL_CPU_TUN_REG_PLL_VCO_GAIN_CLEAR_MASK (0x07000000)
#define PLL_CPU_TUN_REG_PLL_CNT_INT_OFFSET 16
#define PLL_CPU_TUN_REG_PLL_CNT_INT_CLEAR_MASK (0x007f0000)
#define PLL_CPU_TUN_REG_PLL_REG_OD_OFFSET 15
#define PLL_CPU_TUN_REG_PLL_REG_OD_CLEAR_MASK (0x00008000)
#define PLL_CPU_TUN_REG_PLL_B_IN_OFFSET 8
#define PLL_CPU_TUN_REG_PLL_B_IN_CLEAR_MASK (0x00007f00)
#define PLL_CPU_TUN_REG_PLL_REG_OD1_OFFSET 7
#define PLL_CPU_TUN_REG_PLL_REG_OD1_CLEAR_MASK (0x00000080)
#define PLL_CPU_TUN_REG_PLL_B_OUT_OFFSET 0
#define PLL_CPU_TUN_REG_PLL_B_OUT_CLEAR_MASK (0x0000007f)

#define PLL_FUNC_CFG_REG 0x00000404//PLL_FUNC_CFG Register
#define PLL_FUNC_CFG_REG_DCXO_ST_OFFSET 31
#define PLL_FUNC_CFG_REG_DCXO_ST_CLEAR_MASK (0x80000000)
#define PLL_FUNC_CFG_REG_DCXO_ST_SYSTEM_USES_DCXO_40MHZ 0b0
#define PLL_FUNC_CFG_REG_DCXO_ST_SYSTEM_USES_DCXO_24MHZ 0b1
#define PLL_FUNC_CFG_REG_CSI_TEST_EN_OFFSET 28
#define PLL_FUNC_CFG_REG_CSI_TEST_EN_CLEAR_MASK (0x10000000)
#define PLL_FUNC_CFG_REG_VID_TEST_EN_OFFSET 27
#define PLL_FUNC_CFG_REG_VID_TEST_EN_CLEAR_MASK (0x08000000)
#define PLL_FUNC_CFG_REG_PERI_TEST_EN_OFFSET 25
#define PLL_FUNC_CFG_REG_PERI_TEST_EN_CLEAR_MASK (0x02000000)
#define PLL_FUNC_CFG_REG_DDR_TEST_EN_OFFSET 23
#define PLL_FUNC_CFG_REG_DDR_TEST_EN_CLEAR_MASK (0x00800000)
#define PLL_FUNC_CFG_REG_CPU_TEST_EN_OFFSET 22
#define PLL_FUNC_CFG_REG_CPU_TEST_EN_CLEAR_MASK (0x00400000)
#define PLL_FUNC_CFG_REG_CSI_GATE_OFFSET 21
#define PLL_FUNC_CFG_REG_CSI_GATE_CLEAR_MASK (0x00200000)
#define PLL_FUNC_CFG_REG_VID_GATE_OFFSET 20
#define PLL_FUNC_CFG_REG_VID_GATE_CLEAR_MASK (0x00100000)
#define PLL_FUNC_CFG_REG_PERI_GATE_OFFSET 18
#define PLL_FUNC_CFG_REG_PERI_GATE_CLEAR_MASK (0x00040000)
#define PLL_FUNC_CFG_REG_DDR_GATE_OFFSET 16
#define PLL_FUNC_CFG_REG_DDR_GATE_CLEAR_MASK (0x00010000)
#define PLL_FUNC_CFG_REG_CPU_GATE_OFFSET 15
#define PLL_FUNC_CFG_REG_CPU_GATE_CLEAR_MASK (0x00008000)
#define PLL_FUNC_CFG_REG_TEST_EN_OFFSET 14
#define PLL_FUNC_CFG_REG_TEST_EN_CLEAR_MASK (0x00004000)
#define PLL_FUNC_CFG_REG_ST_OFFSET 10
#define PLL_FUNC_CFG_REG_ST_CLEAR_MASK (0x00003c00)
#define PLL_FUNC_CFG_REG_ST_CPU_CKO 0b0000
#define PLL_FUNC_CFG_REG_ST_VIDEOPLL0 0b0001
#define PLL_FUNC_CFG_REG_ST_CSIPLL 0b0010
#define PLL_FUNC_CFG_REG_ST_TIE0 0b0011
#define PLL_FUNC_CFG_REG_ST_DDR_PLL 0b0100
#define PLL_FUNC_CFG_REG_ST_WIFIPLL_FROM_AFE 0b0101
#define PLL_FUNC_CFG_REG_ST_AUDIOPLL1 0b0110
#define PLL_FUNC_CFG_REG_ST_PERIPLL 0b0111
#define PLL_FUNC_CFG_REG_ST_PLL_IN__PLL_REFERENCE_CLOCK 0b1000
#define PLL_FUNC_CFG_REG_ST_TIE00 0b1001
#define PLL_FUNC_CFG_REG_SDIV_OFFSET 8
#define PLL_FUNC_CFG_REG_SDIV_CLEAR_MASK (0x00000300)
#define PLL_FUNC_CFG_REG_PAD_OUT_EN_OFFSET 7
#define PLL_FUNC_CFG_REG_PAD_OUT_EN_CLEAR_MASK (0x00000080)
#define PLL_FUNC_CFG_REG_COMMON_GATE_OFFSET 6
#define PLL_FUNC_CFG_REG_COMMON_GATE_CLEAR_MASK (0x00000040)
#define PLL_FUNC_CFG_REG_CK_TEST_SEL_OFFSET 5
#define PLL_FUNC_CFG_REG_CK_TEST_SEL_CLEAR_MASK (0x00000020)
#define PLL_FUNC_CFG_REG_CK_TEST_SEL_CHOOSE_CK18_DCXO 0b0
#define PLL_FUNC_CFG_REG_CK_TEST_SEL_CHOOSE_TEST_CLK 0b1
#define PLL_FUNC_CFG_REG_MBIAS_EN_OFFSET 4
#define PLL_FUNC_CFG_REG_MBIAS_EN_CLEAR_MASK (0x00000010)
#define PLL_FUNC_CFG_REG_LDO_VSET_OFFSET 1
#define PLL_FUNC_CFG_REG_LDO_VSET_CLEAR_MASK (0x0000000e)
#define PLL_FUNC_CFG_REG_LDO_EN_OFFSET 0
#define PLL_FUNC_CFG_REG_LDO_EN_CLEAR_MASK (0x00000001)

#define HOSC_FREQ_DET 0x00000408//HOSC Freq Detect Register
#define HOSC_FREQ_DET_HOSC_FREQ_DET_OFFSET 4
#define HOSC_FREQ_DET_HOSC_FREQ_DET_CLEAR_MASK (0x00fffff0)
#define HOSC_FREQ_DET_HOSC_FREQ_READY_OFFSET 1
#define HOSC_FREQ_DET_HOSC_FREQ_READY_CLEAR_MASK (0x00000002)
#define HOSC_FREQ_DET_HOSC_OFFSET 0
#define HOSC_FREQ_DET_HOSC_CLEAR_MASK (0x00000001)
#define HOSC_FREQ_DET_HOSC_DISABLE_DETECT 0b0
#define HOSC_FREQ_DET_HOSC_ENABLE_DETECT 0b1

#define REG_CLOCK_01 0x0000040c//REG_CLOCK_01 Register
#define REG_CLOCK_01_SET_TP_IP_OFFSET 7
#define REG_CLOCK_01_SET_TP_IP_CLEAR_MASK (0x00000080)
#define REG_CLOCK_01_SET_DISABLE 0b0
#define REG_CLOCK_01_SET_ENABLE 0b1
#define REG_CLOCK_01_SET_TP_IN_OFFSET 6
#define REG_CLOCK_01_SET_TP_IN_CLEAR_MASK (0x00000040)
#define REG_CLOCK_01_SET_DISABLE 0b0
#define REG_CLOCK_01_SET_ENABLE 0b1
#define REG_CLOCK_01_TEST_P_OFFSET 0
#define REG_CLOCK_01_TEST_P_CLEAR_MASK (0x0000000f)
#define REG_CLOCK_01_TEST_P_NO_TEST 0b0000
#define REG_CLOCK_01_TEST_P_TEST_DCXO_LDO 0b0001
#define REG_CLOCK_01_TEST_P_TEST_BANDGAP_LDO 0b0010
#define REG_CLOCK_01_TEST_P_TEST_CPUPLL_LDO 0b0011
#define REG_CLOCK_01_TEST_P_TEST_VIDEOPLL_LDO 0b0100
#define REG_CLOCK_01_TEST_P_TEST_CSIPLL_LDO 0b0101
#define REG_CLOCK_01_TEST_P_TEST_DDRPLL_LDO 0b0110
#define REG_CLOCK_01_TEST_P_TEST_AUDIOPLL_LDO 0b0111
#define REG_CLOCK_01_TEST_P_TEST_PERIPLL_LDO 0b1000

#define AHB_CLK_REG 0x00000500//AHB CLOCK Register
#define AHB_CLK_REG_AHB_SEL_OFFSET 24
#define AHB_CLK_REG_AHB_SEL_CLEAR_MASK (0x03000000)
#define AHB_CLK_REG_AHB_SEL_HOSC 0b00
#define AHB_CLK_REG_AHB_SEL_PERI_768M 0b01
#define AHB_CLK_REG_AHB_SEL_RC1M 0b10
#define AHB_CLK_REG_AHB_SEL_SYS32K_NO_USE 0b11
#define AHB_CLK_REG_AHB_CLK_DIV_OFFSET 0
#define AHB_CLK_REG_AHB_CLK_DIV_CLEAR_MASK (0x0000001f)

#define APB_CLK_REG 0x00000504//APB CLOCK Register
#define APB_CLK_REG_APB_SEL_OFFSET 24
#define APB_CLK_REG_APB_SEL_CLEAR_MASK (0x03000000)
#define APB_CLK_REG_APB_SEL_HOSC 0b00
#define APB_CLK_REG_APB_SEL_PERI_384M 0b01
#define APB_CLK_REG_APB_SEL_RC1M 0b10
#define APB_CLK_REG_APB_SEL_SYS32K_NO_USE 0b11
#define APB_CLK_REG_APB_CLK_DIV_OFFSET 0
#define APB_CLK_REG_APB_CLK_DIV_CLEAR_MASK (0x0000001f)

#define RTC_APB_CLK_REG 0x00000508//RTC_APB CLOCK Register
#define RTC_APB_CLK_REG_APB_RTC_SEL_OFFSET 24
#define RTC_APB_CLK_REG_APB_RTC_SEL_CLEAR_MASK (0x03000000)
#define RTC_APB_CLK_REG_APB_RTC_SEL_RC1M 0b00
#define RTC_APB_CLK_REG_APB_RTC_SEL_PERI_96M 0b01
#define RTC_APB_CLK_REG_APB_RTC_SEL_HOSC 0b10
#define RTC_APB_CLK_REG_APB_RTC_SEL_SYS32K_NO_USE 0b11
#define RTC_APB_CLK_REG_APB_CLK_RTC_DIV_OFFSET 0
#define RTC_APB_CLK_REG_APB_CLK_RTC_DIV_CLEAR_MASK (0x0000001f)

#define DCXO_CNT_REG 0x00000510//DCXO div32k cnt Register
#define DCXO_CNT_REG_DIV32K_HALFCYCLE_TARGET_OFFSET 0
#define DCXO_CNT_REG_DIV32K_HALFCYCLE_TARGET_CLEAR_MASK (0x000003ff)

#define WLAN_BUS_RSTN_REG 0x00000518//WLAN_BUS_RSTN Register
#define WLAN_BUS_RSTN_REG_WLAN_RESETN_SW_OFFSET 0
#define WLAN_BUS_RSTN_REG_WLAN_RESETN_SW_CLEAR_MASK (0x00000001)
#define WLAN_BUS_RSTN_REG_WLAN_RESETN_SW_ASSERT 0b0
#define WLAN_BUS_RSTN_REG_WLAN_RESETN_SW_DE_ASSERT 0b1

#define BUS_CLK_GATING_REG 0x00000550//CCU_AON Bus CLK Gating Register
#define BUS_CLK_GATING_REG_PWRCTRL_PCLK_EN_OFFSET 6
#define BUS_CLK_GATING_REG_PWRCTRL_PCLK_EN_CLEAR_MASK (0x00000040)
#define BUS_CLK_GATING_REG_PWRCTRL_PCLK_EN_MASK 0b0
#define BUS_CLK_GATING_REG_PWRCTRL_PCLK_EN_PASS 0b1
#define BUS_CLK_GATING_REG_RCCAL_PCLK_EN_OFFSET 2
#define BUS_CLK_GATING_REG_RCCAL_PCLK_EN_CLEAR_MASK (0x00000004)
#define BUS_CLK_GATING_REG_RCCAL_PCLK_EN_MASK 0b0
#define BUS_CLK_GATING_REG_RCCAL_PCLK_EN_PASS 0b1

#define DCXO_CFG_REG 0x00000570//DCXO_CFG Register
#define DCXO_CFG_REG_CLK_REQ_ENB_OFFSET 22
#define DCXO_CFG_REG_CLK_REQ_ENB_CLEAR_MASK (0x00400000)
#define DCXO_CFG_REG_CLK_REQ_ENB_ENABLE 0b0
#define DCXO_CFG_REG_CLK_REQ_ENB_DISABLE 0b1
#define DCXO_CFG_REG_ENHANCE_RF_CLK_OUT_V09_OFFSET 20
#define DCXO_CFG_REG_ENHANCE_RF_CLK_OUT_V09_CLEAR_MASK (0x00300000)
#define DCXO_CFG_REG_ENHANCE_RF_CLK_OUT_V09_8PF 0b00
#define DCXO_CFG_REG_ENHANCE_RF_CLK_OUT_V09_15PF 0b01
#define DCXO_CFG_REG_ENHANCE_RF_CLK_OUT_V09_0 0b1
#define DCXO_CFG_REG_ENHANCE_RF_CLK_OUT_V09_22PF 0b10
#define DCXO_CFG_REG_ENHANCE_RF_CLK_OUT_V09_30PF 0b11
#define DCXO_CFG_REG_XTAL_MODE_V09_OFFSET 19
#define DCXO_CFG_REG_XTAL_MODE_V09_CLEAR_MASK (0x00080000)
#define DCXO_CFG_REG_XTAL_MODE_V09_FOR_EXTERNAL_CLK_D_DIE 0b0
#define DCXO_CFG_REG_XTAL_MODE_V09_INPUT_MODE_A_DIE 0b1
#define DCXO_CFG_REG_DCXO_LDO_INRUSHB_V09_OFFSET 18
#define DCXO_CFG_REG_DCXO_LDO_INRUSHB_V09_CLEAR_MASK (0x00040000)
#define DCXO_CFG_REG_DCXO_TRIM_V09_OFFSET 11
#define DCXO_CFG_REG_DCXO_TRIM_V09_CLEAR_MASK (0x0003f800)
#define DCXO_CFG_REG_DCXO_TRIM_V09_0 0x6
#define DCXO_CFG_REG_DCXO_ICTRL_V09_OFFSET 7
#define DCXO_CFG_REG_DCXO_ICTRL_V09_CLEAR_MASK (0x00000780)
#define DCXO_CFG_REG_DCXO_ICTRL_V09_0 0x3
#define DCXO_CFG_REG_BG_V09_OFFSET 2
#define DCXO_CFG_REG_BG_V09_CLEAR_MASK (0x0000007c)
#define DCXO_CFG_REG_BG_V09_0 0x4
#define DCXO_CFG_REG_MODE_SEL_MUX_OFFSET 1
#define DCXO_CFG_REG_MODE_SEL_MUX_CLEAR_MASK (0x00000002)
#define DCXO_CFG_REG_MODE_SEL_MUX_FROM_SEL_A_N 0b0
#define DCXO_CFG_REG_MODE_SEL_MUX_FROM_INPUT_XTAL_MODE_V09 0b1
#define DCXO_CFG_REG_DCXO_FLAG_OFFSET 0
#define DCXO_CFG_REG_DCXO_FLAG_CLEAR_MASK (0x00000001)
#define DCXO_CFG_REG_DCXO_FLAG_DCXO_SOURCE_FROM_ADIE 0b0
#define DCXO_CFG_REG_DCXO_FLAG_DCXO_SOURCE_FROM_DDIE 0b1

#define DCXO_CFG1_REG 0x00000574//DCXO_CFG1 Register
#define DCXO_CFG1_REG_DCXO_DETECT_MD_OFFSET 13
#define DCXO_CFG1_REG_DCXO_DETECT_MD_CLEAR_MASK (0x00002000)
#define DCXO_CFG1_REG_DCXO_CNT_TG_OFFSET 0
#define DCXO_CFG1_REG_DCXO_CNT_TG_CLEAR_MASK (0x00001fff)

#define APB_SPEC_CLK_REG 0x00000580//APB Special Clock Register
#define APB_SPEC_CLK_REG_APB_SPEC_SEL_OFFSET 24
#define APB_SPEC_CLK_REG_APB_SPEC_SEL_CLEAR_MASK (0x03000000)
#define APB_SPEC_CLK_REG_APB_SPEC_SEL_HOSC 0b00
#define APB_SPEC_CLK_REG_APB_SPEC_SEL_SYS32K_NO_USE 0b01
#define APB_SPEC_CLK_REG_APB_SPEC_SEL_RC1M 0b10
#define APB_SPEC_CLK_REG_APB_SPEC_SEL_PERI_192M 0b11
#define APB_SPEC_CLK_REG_APB_SPEC_CLK_DIV_OFFSET 0
#define APB_SPEC_CLK_REG_APB_SPEC_CLK_DIV_CLEAR_MASK (0x0000001f)

#define E907_CLK_REG 0x00000584//E907 Clock Register
#define E907_CLK_REG_E907_CLK_SEL_OFFSET 24
#define E907_CLK_REG_E907_CLK_SEL_CLEAR_MASK (0x07000000)
#define E907_CLK_REG_E907_CLK_SEL_HOSC 0b000
#define E907_CLK_REG_E907_CLK_SEL_VIDEOPLL2X 0b001
#define E907_CLK_REG_E907_CLK_SEL_RC1M 0b010
#define E907_CLK_REG_E907_CLK_SEL_RC1M0 0b011
#define E907_CLK_REG_E907_CLK_SEL_CPU_PLL 0b100
#define E907_CLK_REG_E907_CLK_SEL_PERI_PLL_1024M 0b101
#define E907_CLK_REG_E907_CLK_SEL_PERI_PLL_614M 0b110
#define E907_CLK_REG_E907_CLK_SEL_PERI_PLL_614M0 0b111
#define E907_CLK_REG_E907_CLK_DIV_OFFSET 0
#define E907_CLK_REG_E907_CLK_DIV_CLEAR_MASK (0x0000001f)

#define A27L2_CLK_REG 0x00000588//A27L2 Clock Register
#define A27L2_CLK_REG_A27L2_CLK_EN_OFFSET 31
#define A27L2_CLK_REG_A27L2_CLK_EN_CLEAR_MASK (0x80000000)
#define A27L2_CLK_REG_A27L2_CLK_EN_CLOCK_IS_OFF 0b0
#define A27L2_CLK_REG_A27L2_CLK_EN_CLOCK_IS_ON 0b1
#define A27L2_CLK_REG_A27L2_CLK_SEL_OFFSET 24
#define A27L2_CLK_REG_A27L2_CLK_SEL_CLEAR_MASK (0x07000000)
#define A27L2_CLK_REG_A27L2_CLK_SEL_HOSC 0b000
#define A27L2_CLK_REG_A27L2_CLK_SEL_VIDEOPLL2X 0b001
#define A27L2_CLK_REG_A27L2_CLK_SEL_RC1M 0b010
#define A27L2_CLK_REG_A27L2_CLK_SEL_RC1M0 0b011
#define A27L2_CLK_REG_A27L2_CLK_SEL_CPU_PLL 0b100
#define A27L2_CLK_REG_A27L2_CLK_SEL_PERI_PLL_1024M 0b101
#define A27L2_CLK_REG_A27L2_CLK_SEL_PERI_PLL_768M 0b110
#define A27L2_CLK_REG_A27L2_CLK_SEL_PERI_PLL_768M0 0b111
#define A27L2_CLK_REG_A27L2_CLK_DIV_OFFSET 0
#define A27L2_CLK_REG_A27L2_CLK_DIV_CLEAR_MASK (0x0000001f)

#define CK_TEST_DIV_REG 0x0000058c//CK_TEST_DIV_register
#define CK_TEST_DIV_REG_CK_TEST_DIV2_OFFSET 16
#define CK_TEST_DIV_REG_CK_TEST_DIV2_CLEAR_MASK (0x001f0000)
#define CK_TEST_DIV_REG_CK_TEST_DIV1_OFFSET 0
#define CK_TEST_DIV_REG_CK_TEST_DIV1_CLEAR_MASK (0x0000001f)

/* CCU APP */
#define DRAM_CLK_REG 0x00000004//DRAM_Clock Register
#define DRAM_CLK_REG_DRAM_CLK_GATING_OFFSET 31
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLEAR_MASK (0x80000000)
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_OFF 0b0
#define DRAM_CLK_REG_DRAM_CLK_GATING_CLOCK_IS_ON 0b1
#define DRAM_CLK_REG_DRAM_UPD_OFFSET 27
#define DRAM_CLK_REG_DRAM_UPD_CLEAR_MASK (0x08000000)
#define DRAM_CLK_REG_DRAM_UPD_INVALID 0b0
#define DRAM_CLK_REG_DRAM_UPD_VALID 0b1
#define DRAM_CLK_REG_DRAM_CLK_SEL_OFFSET 24
#define DRAM_CLK_REG_DRAM_CLK_SEL_CLEAR_MASK (0x07000000)
#define DRAM_CLK_REG_DRAM_CLK_SEL_CLK_HOSC 0b000
#define DRAM_CLK_REG_DRAM_CLK_SEL_DDRPLL 0b001
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI_1024M 0b010
#define DRAM_CLK_REG_DRAM_CLK_SEL_PERI_768M 0b011
#define DRAM_CLK_REG_DRAM_DIV2_OFFSET 16
#define DRAM_CLK_REG_DRAM_DIV2_CLEAR_MASK (0x00030000)
#define DRAM_CLK_REG_DRAM_DIV2_1 0b00
#define DRAM_CLK_REG_DRAM_DIV2_2 0b01
#define DRAM_CLK_REG_DRAM_DIV2_4 0b10
#define DRAM_CLK_REG_DRAM_DIV2_8 0b11
#define DRAM_CLK_REG_DRAM_DIV1_OFFSET 0
#define DRAM_CLK_REG_DRAM_DIV1_CLEAR_MASK (0x0000001f)

#define E907_TS_Clock_REG 0x0000000c//E907_TS_Clock Register
#define E907_TS_CLK_EN_OFFSET 31
#define E907_TS_CLK_EN_CLEAR_MASK (0x80000000)
#define E907_TS_CLK_EN_CLOCK_IS_OFF 0b0
#define E907_TS_CLK_EN_CLOCK_IS_ON 0b1
#define E907_TS_CLK_SEL_OFFSET 24
#define E907_TS_CLK_SEL_CLEAR_MASK (0x01000000)
#define E907_TS_CLK_SEL_HOSC 0b0
#define E907_TS_CLK_SEL_SYS_32K 0b1

#define A27L2_MT_Clock_REG 0x00000010//A27L2_MT_Clock Register
#define REG_A27L2_MT_CLK_EN_OFFSET 31
#define A27L2_MT_CLK_EN_CLEAR_MASK (0x80000000)
#define A27L2_MT_CLK_EN_CLOCK_IS_OFF 0b0
#define A27L2_MT_CLK_EN_CLOCK_IS_ON 0b1
#define A27L2_MT_CLK_SEL_OFFSET 24
#define A27L2_MT_CLK_SEL_CLEAR_MASK (0x01000000)
#define A27L2_MT_CLK_SEL_HOSC 0b0
#define A27L2_MT_CLK_SEL_SYS_32K 0b1

#define SMHC_CTRL0_CLK_REG 0x00000014//SMHC_CTRL_Clock Register
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_EN_OFFSET 31
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_EN_CLEAR_MASK (0x80000000)
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_EN_CLOCK_IS_OFF 0b0
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_EN_CLOCK_IS_ON 0b1
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_SEL_OFFSET 24
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_SEL_CLEAR_MASK (0x07000000)
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_SEL_HOSC 0b000
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_SEL_PERI_192M 0b001
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_SEL_PERI_219M 0b010
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_SEL_DDRPLL 0b100
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_SEL_VIDEPLL2X 0b101
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_DIV2_OFFSET 16
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_DIV2_CLEAR_MASK (0x001f0000)
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_DIV1_OFFSET 0
#define SMHC_CTRL0_CLK_REG_SMHC_CTRL0_CLK_DIV1_CLEAR_MASK (0x0000001f)

#define SS_CLK_REG 0x00000018//SS_Clock Register
#define SS_CLK_REG_SS_CLK_EN_OFFSET 31
#define SS_CLK_REG_SS_CLK_EN_CLEAR_MASK (0x80000000)
#define SS_CLK_REG_SS_CLK_EN_CLOCK_IS_OFF 0b0
#define SS_CLK_REG_SS_CLK_EN_CLOCK_IS_ON 0b1
#define SS_CLK_REG_SS_CLK_SEL_OFFSET 24
#define SS_CLK_REG_SS_CLK_SEL_CLEAR_MASK (0x01000000)
#define SS_CLK_REG_SS_CLK_SEL_HOSC 0b0
#define SS_CLK_REG_SS_CLK_SEL_PERI_118M 0b1
#define SS_CLK_REG_SS_CLK_DIV_OFFSET 0
#define SS_CLK_REG_SS_CLK_DIV_CLEAR_MASK (0x0000001f)

#define SPI_CLK_REG 0x0000001c//SPI_Clock Register
#define SPI_CLK_REG_SPI_SCLK_EN_OFFSET 31
#define SPI_CLK_REG_SPI_SCLK_EN_CLEAR_MASK (0x80000000)
#define SPI_CLK_REG_SPI_SCLK_EN_CLOCK_IS_OFF 0b0
#define SPI_CLK_REG_SPI_SCLK_EN_CLOCK_IS_ON 0b1
#define SPI_CLK_REG_SPI_SCLK_SEL_OFFSET 24
#define SPI_CLK_REG_SPI_SCLK_SEL_CLEAR_MASK (0x07000000)
#define SPI_CLK_REG_SPI_SCLK_SEL_HOSC 0b000
#define SPI_CLK_REG_SPI_SCLK_SEL_PERI_307M 0b001
#define SPI_CLK_REG_SPI_SCLK_SEL_PERI_236M 0b010
#define SPI_CLK_REG_SPI_SCLK_SEL_PERI_48M 0b100
#define SPI_CLK_REG_SPI_SCLK_SEL_CSIPLL2X 0b101
#define SPI_CLK_REG_SPI_SCLK_DIV2_OFFSET 16
#define SPI_CLK_REG_SPI_SCLK_DIV2_CLEAR_MASK (0x00030000)
#define SPI_CLK_REG_SPI_SCLK_DIV2_1 0b00
#define SPI_CLK_REG_SPI_SCLK_DIV2_2 0b01
#define SPI_CLK_REG_SPI_SCLK_DIV2_4 0b10
#define SPI_CLK_REG_SPI_SCLK_DIV2_8 0b11
#define SPI_CLK_REG_SPI_SCLK_DIV1_OFFSET 0
#define SPI_CLK_REG_SPI_SCLK_DIV1_CLEAR_MASK (0x0000000f)

#define SPIF_CLK_REG 0x00000020//SPIF_Clock Register
#define SPIF_CLK_REG_SPIF_SCLK_EN_OFFSET 31
#define SPIF_CLK_REG_SPIF_SCLK_EN_CLEAR_MASK (0x80000000)
#define SPIF_CLK_REG_SPIF_SCLK_EN_CLOCK_IS_OFF 0b0
#define SPIF_CLK_REG_SPIF_SCLK_EN_CLOCK_IS_ON 0b1
#define SPIF_CLK_REG_SPIF_SCLK_SEL_OFFSET 24
#define SPIF_CLK_REG_SPIF_SCLK_SEL_CLEAR_MASK (0x03000000)
#define SPIF_CLK_REG_SPIF_SCLK_SEL_HOSC 0b00
#define SPIF_CLK_REG_SPIF_SCLK_SEL_PERI_512M 0b01
#define SPIF_CLK_REG_SPIF_SCLK_SEL_PERI_384M 0b10
#define SPIF_CLK_REG_SPIF_SCLK_SEL_PERI_307M 0b11
#define SPIF_CLK_REG_SPIF_SCLK_DIV2_OFFSET 16
#define SPIF_CLK_REG_SPIF_SCLK_DIV2_CLEAR_MASK (0x00030000)
#define SPIF_CLK_REG_SPIF_SCLK_DIV2_1 0b00
#define SPIF_CLK_REG_SPIF_SCLK_DIV2_2 0b01
#define SPIF_CLK_REG_SPIF_SCLK_DIV2_4 0b10
#define SPIF_CLK_REG_SPIF_SCLK_DIV2_8 0b11
#define SPIF_CLK_REG_SPIF_SCLK_DIV1_OFFSET 0
#define SPIF_CLK_REG_SPIF_SCLK_DIV1_CLEAR_MASK (0x0000000f)

#define MCSI_CLK_REG 0x00000024//MCSI_Clock Register
#define MCSI_CLK_REG_MCSI_CLK_EN_OFFSET 31
#define MCSI_CLK_REG_MCSI_CLK_EN_CLEAR_MASK (0x80000000)
#define MCSI_CLK_REG_MCSI_CLK_EN_CLOCK_IS_OFF 0b0
#define MCSI_CLK_REG_MCSI_CLK_EN_CLOCK_IS_ON 0b1
#define MCSI_CLK_REG_MCSI_CLK_SEL_OFFSET 24
#define MCSI_CLK_REG_MCSI_CLK_SEL_CLEAR_MASK (0x07000000)
#define MCSI_CLK_REG_MCSI_CLK_SEL_PERI_236M 0b000
#define MCSI_CLK_REG_MCSI_CLK_SEL_PERI_307M 0b001
#define MCSI_CLK_REG_MCSI_CLK_SEL_PERI_384M 0b010
#define MCSI_CLK_REG_MCSI_CLK_SEL_VIDEOPLL4X 0b100
#define MCSI_CLK_REG_MCSI_CLK_SEL_CSIPLL4X 0b101
#define MCSI_CLK_REG_MCSI_CLK_DIV_OFFSET 0
#define MCSI_CLK_REG_MCSI_CLK_DIV_CLEAR_MASK (0x0000001f)

#define CSI_MASTER0_CLK_REG 0x00000028//CSI_MASTER0_Clock Register
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_EN_OFFSET 31
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_EN_CLEAR_MASK (0x80000000)
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_EN_CLOCK_IS_OFF 0b0
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_EN_CLOCK_IS_ON 0b1
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_SEL_OFFSET 24
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_SEL_CLEAR_MASK (0x07000000)
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_SEL_HOSC 0b000
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_SEL_CSIPLL4X 0b001
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_SEL_VIDEOPLL4X 0b010
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_SEL_PERI_1024M 0b100
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_SEL_PERI_24M 0b101
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_DIV2_OFFSET 16
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_DIV2_CLEAR_MASK (0x00030000)
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_DIV2_1 0b00
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_DIV2_2 0b01
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_DIV2_4 0b10
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_DIV2_8 0b11
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_DIV1_OFFSET 0
#define CSI_MASTER0_CLK_REG_CSI_MASTER0_CLK_DIV1_CLEAR_MASK (0x0000001f)

#define CSI_MASTER1_CLK_REG 0x0000002c//CSI_MASTER1_Clock Register
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_EN_OFFSET 31
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_EN_CLEAR_MASK (0x80000000)
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_EN_CLOCK_IS_OFF 0b0
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_EN_CLOCK_IS_ON 0b1
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_SEL_OFFSET 24
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_SEL_CLEAR_MASK (0x07000000)
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_SEL_HOSC 0b000
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_SEL_CSIPLL4X 0b001
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_SEL_VIDEOPLL4X 0b010
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_SEL_PERI_1024M 0b100
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_SEL_PERI_24M 0b101
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_DIV2_OFFSET 16
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_DIV2_CLEAR_MASK (0x00030000)
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_DIV2_1 0b00
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_DIV2_2 0b01
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_DIV2_4 0b10
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_DIV2_8 0b11
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_DIV1_OFFSET 0
#define CSI_MASTER1_CLK_REG_CSI_MASTER1_CLK_DIV1_CLEAR_MASK (0x0000001f)

#define SPI2_CLK_REG 0x00000030//SPI2_Clock Register
#define SPI2_CLK_REG_SPI2_SCLK_EN_OFFSET 31
#define SPI2_CLK_REG_SPI2_SCLK_EN_CLEAR_MASK (0x80000000)
#define SPI2_CLK_REG_SPI2_SCLK_EN_CLOCK_IS_OFF 0b0
#define SPI2_CLK_REG_SPI2_SCLK_EN_CLOCK_IS_ON 0b1
#define SPI2_CLK_REG_SPI_SCLK_SEL_OFFSET 24
#define SPI2_CLK_REG_SPI_SCLK_SEL_CLEAR_MASK (0x07000000)
#define SPI2_CLK_REG_SPI_SCLK_SEL_HOSC 0b000
#define SPI2_CLK_REG_SPI_SCLK_SEL_PERI_307M 0b001
#define SPI2_CLK_REG_SPI_SCLK_SEL_PERI_236M 0b010
#define SPI2_CLK_REG_SPI_SCLK_SEL_PERI_48M 0b100
#define SPI2_CLK_REG_SPI_SCLK_SEL_CSIPLL2X 0b101
#define SPI2_CLK_REG_SPI2_SCLK_DIV2_OFFSET 16
#define SPI2_CLK_REG_SPI2_SCLK_DIV2_CLEAR_MASK (0x00030000)
#define SPI2_CLK_REG_SPI2_SCLK_DIV2_1 0b00
#define SPI2_CLK_REG_SPI2_SCLK_DIV2_2 0b01
#define SPI2_CLK_REG_SPI2_SCLK_DIV2_4 0b10
#define SPI2_CLK_REG_SPI2_SCLK_DIV2_8 0b11
#define SPI2_CLK_REG_SPI2_SCLK_DIV1_OFFSET 0
#define SPI2_CLK_REG_SPI2_SCLK_DIV1_CLEAR_MASK (0x0000000f)

#define TCON_LCD_CLK_REG 0x00000034//TCON_LCD_Clock Register
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_EN_OFFSET 31
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_EN_CLEAR_MASK (0x80000000)
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_EN_CLOCK_IS_OFF 0b0
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_EN_CLOCK_IS_ON 0b1
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_SEL_OFFSET 24
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_SEL_CLEAR_MASK (0x03000000)
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_SEL_VIDEOPLL4X 0b00
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_SEL_PERI_512M 0b01
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_SEL_CSIPLL4X 0b10
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_SEL_AUDIOPLL_DIV2 0b11
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_DIV2_OFFSET 16
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_DIV2_CLEAR_MASK (0x00030000)
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_DIV2_1 0b00
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_DIV2_2 0b01
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_DIV2_4 0b10
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_DIV2_8 0b11
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_DIV1_OFFSET 0
#define TCON_LCD_CLK_REG_TCON_LCD_CLK_DIV1_CLEAR_MASK (0x0000000f)

#define DE_CLK_REG 0x00000038//DE_Clock Register
#define DE_CLK_REG_DE_CLK_EN_OFFSET 31
#define DE_CLK_REG_DE_CLK_EN_CLEAR_MASK (0x80000000)
#define DE_CLK_REG_DE_CLK_EN_CLOCK_IS_OFF 0b0
#define DE_CLK_REG_DE_CLK_EN_CLOCK_IS_ON 0b1
#define DE_CLK_REG_DE_CLK_SEL_OFFSET 24
#define DE_CLK_REG_DE_CLK_SEL_CLEAR_MASK (0x01000000)
#define DE_CLK_REG_DE_CLK_SEL_PERI_307M 0b0
#define DE_CLK_REG_DE_CLK_SEL_VIDEOPLL1X 0b1
#define DE_CLK_REG_DE_CLK_DIV_OFFSET 0
#define DE_CLK_REG_DE_CLK_DIV_CLEAR_MASK (0x0000001f)

#define G2D_CLK_REG 0x0000003c//G2D_Clock Register
#define G2D_CLK_REG_G2D_CLK_EN_OFFSET 31
#define G2D_CLK_REG_G2D_CLK_EN_CLEAR_MASK (0x80000000)
#define G2D_CLK_REG_G2D_CLK_EN_CLOCK_IS_OFF 0b0
#define G2D_CLK_REG_G2D_CLK_EN_CLOCK_IS_ON 0b1
#define G2D_CLK_REG_G2D_CLK_SEL_OFFSET 24
#define G2D_CLK_REG_G2D_CLK_SEL_CLEAR_MASK (0x01000000)
#define G2D_CLK_REG_G2D_CLK_SEL_PERI_307M 0b0
#define G2D_CLK_REG_G2D_CLK_SEL_VIDEOPLL1X 0b1
#define G2D_CLK_REG_G2D_CLK_DIV_OFFSET 0
#define G2D_CLK_REG_G2D_CLK_DIV_CLEAR_MASK (0x0000001f)

#define GPADC_CLK_REG 0x00000040//GPADC Clock Register
#define GPADC_CLK_REG_GPADC_CLK_EN_OFFSET 31
#define GPADC_CLK_REG_GPADC_CLK_EN_CLEAR_MASK (0x80000000)
#define GPADC_CLK_REG_GPADC_CLK_EN_CLOCK_IS_OFF 0b0
#define GPADC_CLK_REG_GPADC_CLK_EN_CLOCK_IS_ON 0b1
#define GPADC_CLK_REG_GPADC_CLK_SEL_OFFSET 24
#define GPADC_CLK_REG_GPADC_CLK_SEL_CLEAR_MASK (0x03000000)
#define GPADC_CLK_REG_GPADC_CLK_SEL_CLK_24M 0b00
#define GPADC_CLK_REG_GPADC_CLK_SEL_HOSC 0b01
#define GPADC_CLK_REG_GPADC_CLK_SEL_SYS32K 0b10
#define GPADC_CLK_REG_GPADC_CLK_DIV_OFFSET 0
#define GPADC_CLK_REG_GPADC_CLK_DIV_CLEAR_MASK (0x0000001f)

#define VE_CLK_REG 0x00000044//VE Clock Register
#define VE_CLK_REG_VE_CLK_EN_OFFSET 31
#define VE_CLK_REG_VE_CLK_EN_CLEAR_MASK (0x80000000)
#define VE_CLK_REG_VE_CLK_EN_CLOCK_IS_OFF 0b0
#define VE_CLK_REG_VE_CLK_EN_CLOCK_IS_ON 0b1
#define VE_CLK_REG_VE_CLK_SEL_OFFSET 24
#define VE_CLK_REG_VE_CLK_SEL_CLEAR_MASK (0x07000000)
#define VE_CLK_REG_VE_CLK_DIV_OFFSET 0
#define VE_CLK_REG_VE_CLK_DIV_CLEAR_MASK (0x00000007)

#define SMHC_CTRL1_CLK_REG 0x0000005c//SMHC_CTRL2_Clock Register
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_EN_OFFSET 31
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_EN_CLEAR_MASK (0x80000000)
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_EN_CLOCK_IS_OFF 0b0
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_EN_CLOCK_IS_ON 0b1
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_SEL_OFFSET 24
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_SEL_CLEAR_MASK (0x07000000)
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_SEL_HOSC 0b000
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_SEL_PERI_192M 0b001
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_SEL_PERI_219M 0b010
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_SEL_DDRPLL 0b100
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_SEL_VIDEPLL2X 0b101
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_DIV2_OFFSET 16
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_DIV2_CLEAR_MASK (0x001f0000)
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_DIV1_OFFSET 0
#define SMHC_CTRL1_CLK_REG_SMHC_CTRL1_CLK_DIV1_CLEAR_MASK (0x0000001f)

#define AUDIO_DIV_CLK_REG 0x00000060//AUDIO Divider Clock Register
#define AUDIO_DIV_CLK_REG_AUDIOPLL4X_SEL_OFFSET 26
#define AUDIO_DIV_CLK_REG_AUDIOPLL4X_SEL_CLEAR_MASK (0x0c000000)
#define AUDIO_DIV_CLK_REG_AUDIOPLL4X_SEL_PERI_1536M 0b00
#define AUDIO_DIV_CLK_REG_AUDIOPLL4X_SEL_CPUPLL 0b01
#define AUDIO_DIV_CLK_REG_AUDIOPLL4X_SEL_VIDEOPLL2X 0b10
#define AUDIO_DIV_CLK_REG_AUDIOPLL1X_SEL_OFFSET 24
#define AUDIO_DIV_CLK_REG_AUDIOPLL1X_SEL_CLEAR_MASK (0x03000000)
#define AUDIO_DIV_CLK_REG_AUDIOPLL1X_SEL_PERI_614M 0b00
#define AUDIO_DIV_CLK_REG_AUDIOPLL1X_SEL_CPUPLL 0b01
#define AUDIO_DIV_CLK_REG_AUDIOPLL1X_SEL_VIDEOPLL2X 0b10
#define AUDIO_DIV_CLK_REG_AUDIOPLL4X_DIV_OFFSET 5
#define AUDIO_DIV_CLK_REG_AUDIOPLL4X_DIV_CLEAR_MASK (0x000003e0)
#define AUDIO_DIV_CLK_REG_AUDIOPLL1X_DIV_OFFSET 0
#define AUDIO_DIV_CLK_REG_AUDIOPLL1X_DIV_CLEAR_MASK (0x0000001f)

#define SPI1_CLK_REG 0x00000064//SPI1_Clock Register
#define SPI1_CLK_REG_SPI1_SCLK_EN_OFFSET 31
#define SPI1_CLK_REG_SPI1_SCLK_EN_CLEAR_MASK (0x80000000)
#define SPI1_CLK_REG_SPI1_SCLK_EN_CLOCK_IS_OFF 0b0
#define SPI1_CLK_REG_SPI1_SCLK_EN_CLOCK_IS_ON 0b1
#define SPI1_CLK_REG_SPI_SCLK_SEL_OFFSET 24
#define SPI1_CLK_REG_SPI_SCLK_SEL_CLEAR_MASK (0x07000000)
#define SPI1_CLK_REG_SPI_SCLK_SEL_HOSC 0b000
#define SPI1_CLK_REG_SPI_SCLK_SEL_PERI_307M 0b001
#define SPI1_CLK_REG_SPI_SCLK_SEL_PERI_236M 0b010
#define SPI1_CLK_REG_SPI_SCLK_SEL_PERI_48M 0b100
#define SPI1_CLK_REG_SPI_SCLK_SEL_CSIPLL2X 0b101
#define SPI1_CLK_REG_SPI1_SCLK_DIV2_OFFSET 16
#define SPI1_CLK_REG_SPI1_SCLK_DIV2_CLEAR_MASK (0x00030000)
#define SPI1_CLK_REG_SPI1_SCLK_DIV2_1 0b00
#define SPI1_CLK_REG_SPI1_SCLK_DIV2_2 0b01
#define SPI1_CLK_REG_SPI1_SCLK_DIV2_4 0b10
#define SPI1_CLK_REG_SPI1_SCLK_DIV2_8 0b11
#define SPI1_CLK_REG_SPI1_SCLK_DIV1_OFFSET 0
#define SPI1_CLK_REG_SPI1_SCLK_DIV1_CLEAR_MASK (0x0000000f)

#define E907_R_CLK_REG 0x00000068//E907_RCLK_Register
#define E907_R_CLK_REG_E907_RCLK_DIV_OFFSET 0
#define E907_R_CLK_REG_E907_RCLK_DIV_CLEAR_MASK (0x00000003)
#define E907_R_CLK_REG_E907_RCLK_DIV_DIV1 0b00
#define E907_R_CLK_REG_E907_RCLK_DIV_DIV2 0b01
#define E907_R_CLK_REG_E907_RCLK_DIV_DIV3 0b10
#define E907_R_CLK_REG_E907_RCLK_DIV_DIV4 0b11

#define GMAC_CLK_FANOUT_REG 0x0000006c//GMAC_CLK_FANOUT_Register
#define GMAC_CLK_FANOUT_REG_GMAC_APB_CLK_DIV2_OFFSET 24
#define GMAC_CLK_FANOUT_REG_GMAC_APB_CLK_DIV2_CLEAR_MASK (0x1f000000)
#define GMAC_CLK_FANOUT_REG_GMAC_APB_CLK_DIV1_OFFSET 19
#define GMAC_CLK_FANOUT_REG_GMAC_APB_CLK_DIV1_CLEAR_MASK (0x00f80000)
#define GMAC_CLK_FANOUT_REG_GMAC_APB_SRCCLK_EN_OFFSET 18
#define GMAC_CLK_FANOUT_REG_GMAC_APB_SRCCLK_EN_CLEAR_MASK (0x00040000)
#define GMAC_CLK_FANOUT_REG_GMAC_APB_SRCCLK_EN_CLOCK_IS_OFF 0b0
#define GMAC_CLK_FANOUT_REG_GMAC_APB_SRCCLK_EN_CLOCK_IS_ON 0b1
#define GMAC_CLK_FANOUT_REG_GMAC_16M_SRCCLK_EN_OFFSET 17
#define GMAC_CLK_FANOUT_REG_GMAC_16M_SRCCLK_EN_CLEAR_MASK (0x00020000)
#define GMAC_CLK_FANOUT_REG_GMAC_16M_SRCCLK_EN_CLOCK_IS_OFF 0b0
#define GMAC_CLK_FANOUT_REG_GMAC_16M_SRCCLK_EN_CLOCK_IS_ON 0b1
#define GMAC_CLK_FANOUT_REG_GMAC_32K_CLK_SEL_OFFSET 16
#define GMAC_CLK_FANOUT_REG_GMAC_32K_CLK_SEL_CLEAR_MASK (0x00010000)
#define GMAC_CLK_FANOUT_REG_GMAC_32K_CLK_SEL_SOURCE_FROM_SYS_32K_APP 0b0
#define GMAC_CLK_FANOUT_REG_GMAC_32K_CLK_SEL_SOURCE_FROM_DCXO_DIV_32K_APP 0b1
#define GMAC_CLK_FANOUT_REG_GMAC_32K_SRCCLK_EN_OFFSET 15
#define GMAC_CLK_FANOUT_REG_GMAC_32K_SRCCLK_EN_CLEAR_MASK (0x00008000)
#define GMAC_CLK_FANOUT_REG_GMAC_32K_SRCCLK_EN_CLOCK_IS_OFF 0b0
#define GMAC_CLK_FANOUT_REG_GMAC_32K_SRCCLK_EN_CLOCK_IS_ON 0b1
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_DIV2_OFFSET 13
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_DIV2_CLEAR_MASK (0x00006000)
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_DIV2_1 0b00
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_DIV2_2 0b01
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_DIV2_4 0b10
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_DIV2_8 0b11
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_DIV1_OFFSET 8
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_DIV1_CLEAR_MASK (0x00001f00)
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_SEL_OFFSET 6
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_SEL_CLEAR_MASK (0x000000c0)
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_SEL_SOURCE_FROM_VIDEOPLL1X 0b00
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_SEL_SOURCE_FROM_CSIPLL4X 0b01
#define GMAC_CLK_FANOUT_REG_GMAC_27M_CLK_SEL_SOURCE_FROM_DCXO 0b10
#define GMAC_CLK_FANOUT_REG_GMAC_27M_SRCCLK_EN_OFFSET 5
#define GMAC_CLK_FANOUT_REG_GMAC_27M_SRCCLK_EN_CLEAR_MASK (0x00000020)
#define GMAC_CLK_FANOUT_REG_GMAC_27M_SRCCLK_EN_CLOCK_IS_OFF 0b0
#define GMAC_CLK_FANOUT_REG_GMAC_27M_SRCCLK_EN_CLOCK_IS_ON 0b1
#define GMAC_CLK_FANOUT_REG_GMAC_24M_CLK_SEL_OFFSET 4
#define GMAC_CLK_FANOUT_REG_GMAC_24M_CLK_SEL_CLEAR_MASK (0x00000010)
#define GMAC_CLK_FANOUT_REG_GMAC_24M_CLK_SEL_SOURCE_FROM_PERIPLL_24M 0b0
#define GMAC_CLK_FANOUT_REG_GMAC_24M_CLK_SEL_SOURCE_FROM_DCXO 0b1
#define GMAC_CLK_FANOUT_REG_GMAC_24M_SRCCLK_EN_OFFSET 3
#define GMAC_CLK_FANOUT_REG_GMAC_24M_SRCCLK_EN_CLEAR_MASK (0x00000008)
#define GMAC_CLK_FANOUT_REG_GMAC_24M_SRCCLK_EN_CLOCK_IS_OFF 0b0
#define GMAC_CLK_FANOUT_REG_GMAC_24M_SRCCLK_EN_CLOCK_IS_ON 0b1

#define GMAC_25M_CLK_REG 0x00000074//GMAC_25M_CLK_REG
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_EN_OFFSET 31
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_EN_CLEAR_MASK (0x80000000)
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_EN_CLOCK_IS_OFF 0b0
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_EN_CLOCK_IS_ON 0b1
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SEL_OFFSET 24
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SEL_CLEAR_MASK (0x03000000)
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SEL_HOSC 0b00
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SEL_CSIPLL2X 0b01
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_SEL_CPUPLL 0b10
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_DIV2_OFFSET 16
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_DIV2_CLEAR_MASK (0x001f0000)
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_DIV1_OFFSET 0
#define GMAC_25M_CLK_REG_GMAC_25M_CLK_DIV1_CLEAR_MASK (0x0000001f)

#define CCU_APP_CLK_REG 0x0000007c//CCU_APP_Clock Register
#define CCU_APP_CLK_REG_A27L2_BUSCLKDIV_OFFSET 8
#define CCU_APP_CLK_REG_A27L2_BUSCLKDIV_CLEAR_MASK (0x00000300)
#define CCU_APP_CLK_REG_A27L2_BUSCLKDIV_DIV1 0b00
#define CCU_APP_CLK_REG_A27L2_BUSCLKDIV_DIV2 0b01
#define CCU_APP_CLK_REG_A27L2_BUSCLKDIV_DIV3 0b10
#define CCU_APP_CLK_REG_A27L2_BUSCLKDIV_DIV4 0b11
#define CCU_APP_CLK_REG_A27L2_CFG_CLKEN_OFFSET 7
#define CCU_APP_CLK_REG_A27L2_CFG_CLKEN_CLEAR_MASK (0x00000080)
#define CCU_APP_CLK_REG_A27L2_CFG_CLKEN_CLOCK_IS_OFF 0b0
#define CCU_APP_CLK_REG_A27L2_CFG_CLKEN_CLOCK_IS_ON 0b1
#define CCU_APP_CLK_REG_A27_MSGBOX_HCLKEN_OFFSET 6
#define CCU_APP_CLK_REG_A27_MSGBOX_HCLKEN_CLEAR_MASK (0x00000040)
#define CCU_APP_CLK_REG_A27_MSGBOX_HCLKEN_CLOCK_IS_OFF 0b0
#define CCU_APP_CLK_REG_A27_MSGBOX_HCLKEN_CLOCK_IS_ON 0b1
#define CCU_APP_CLK_REG_WIEGAND_24M_EN_OFFSET 4
#define CCU_APP_CLK_REG_WIEGAND_24M_EN_CLEAR_MASK (0x00000010)
#define CCU_APP_CLK_REG_WIEGAND_24M_EN_CLOCK_IS_OFF 0b0
#define CCU_APP_CLK_REG_WIEGAND_24M_EN_CLOCK_IS_ON 0b1
#define CCU_APP_CLK_REG_CLK24M_USB_EN_OFFSET 3
#define CCU_APP_CLK_REG_CLK24M_USB_EN_CLEAR_MASK (0x00000008)
#define CCU_APP_CLK_REG_CLK24M_USB_EN_CLOCK_IS_OFF 0b0
#define CCU_APP_CLK_REG_CLK24M_USB_EN_CLOCK_IS_ON 0b1
#define CCU_APP_CLK_REG_CLK12M_USB_EN_OFFSET 2
#define CCU_APP_CLK_REG_CLK12M_USB_EN_CLEAR_MASK (0x00000004)
#define CCU_APP_CLK_REG_CLK12M_USB_EN_CLOCK_IS_OFF 0b0
#define CCU_APP_CLK_REG_CLK12M_USB_EN_CLOCK_IS_ON 0b1
#define CCU_APP_CLK_REG_CLK48M_USB_EN_OFFSET 1
#define CCU_APP_CLK_REG_CLK48M_USB_EN_CLEAR_MASK (0x00000002)
#define CCU_APP_CLK_REG_CLK48M_USB_EN_CLOCK_IS_OFF 0b0
#define CCU_APP_CLK_REG_CLK48M_USB_EN_CLOCK_IS_ON 0b1
#define CCU_APP_CLK_REG_AVS_CLK_EN_OFFSET 0
#define CCU_APP_CLK_REG_AVS_CLK_EN_CLEAR_MASK (0x00000001)
#define CCU_APP_CLK_REG_AVS_CLK_EN_CLOCK_IS_OFF 0b0
#define CCU_APP_CLK_REG_AVS_CLK_EN_CLOCK_IS_ON 0b1

#define BUS_CLK_GATING0_REG 0x00000080//CCU_APP Bus CLK Gating0 Register
#define BUS_CLK_GATING0_REG_DPSS_TOP_CLK_EN_OFFSET 31
#define BUS_CLK_GATING0_REG_DPSS_TOP_CLK_EN_CLEAR_MASK (0x80000000)
#define BUS_CLK_GATING0_REG_DPSS_TOP_CLK_EN_MASK 0b0
#define BUS_CLK_GATING0_REG_DPSS_TOP_CLK_EN_PASS 0b1
#define BUS_CLK_GATING0_REG_GPIO_PCLK_EN_OFFSET 30
#define BUS_CLK_GATING0_REG_GPIO_PCLK_EN_CLEAR_MASK (0x40000000)
#define BUS_CLK_GATING0_REG_GPIO_PCLK_EN_MASK 0b0
#define BUS_CLK_GATING0_REG_GPIO_PCLK_EN_PASS 0b1
#define BUS_CLK_GATING0_REG_WKT_PCLK_EN_OFFSET 29
#define BUS_CLK_GATING0_REG_WKT_PCLK_EN_CLEAR_MASK (0x20000000)
#define BUS_CLK_GATING0_REG_WKT_PCLK_EN_MASK 0b0
#define BUS_CLK_GATING0_REG_WKT_PCLK_EN_PASS 0b1
#define BUS_CLK_GATING0_REG_MCSI_AHB_CLK_EN_OFFSET 28
#define BUS_CLK_GATING0_REG_MCSI_AHB_CLK_EN_CLEAR_MASK (0x10000000)
#define BUS_CLK_GATING0_REG_MCSI_AHB_CLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_MCSI_AHB_CLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_MCSI_MBUS_CLK_EN_OFFSET 27
#define BUS_CLK_GATING0_REG_MCSI_MBUS_CLK_EN_CLEAR_MASK (0x08000000)
#define BUS_CLK_GATING0_REG_MCSI_MBUS_CLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_MCSI_MBUS_CLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_VID_OUT_AHB_CLK_EN_OFFSET 26
#define BUS_CLK_GATING0_REG_VID_OUT_AHB_CLK_EN_CLEAR_MASK (0x04000000)
#define BUS_CLK_GATING0_REG_VID_OUT_AHB_CLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_VID_OUT_AHB_CLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_VID_OUT_MBUS_CLK_EN_OFFSET 25
#define BUS_CLK_GATING0_REG_VID_OUT_MBUS_CLK_EN_CLEAR_MASK (0x02000000)
#define BUS_CLK_GATING0_REG_VID_OUT_MBUS_CLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_VID_OUT_MBUS_CLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_GMAC_HCLK_EN_OFFSET 24
#define BUS_CLK_GATING0_REG_GMAC_HCLK_EN_CLEAR_MASK (0x01000000)
#define BUS_CLK_GATING0_REG_GMAC_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_GMAC_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_USBOHCI_BUSCLKEN_OFFSET 22
#define BUS_CLK_GATING0_REG_USBOHCI_BUSCLKEN_CLEAR_MASK (0x00400000)
#define BUS_CLK_GATING0_REG_USBOHCI_BUSCLKEN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_USBOHCI_BUSCLKEN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_USBEHCI_BUSCLKEN_OFFSET 21
#define BUS_CLK_GATING0_REG_USBEHCI_BUSCLKEN_CLEAR_MASK (0x00200000)
#define BUS_CLK_GATING0_REG_USBEHCI_BUSCLKEN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_USBEHCI_BUSCLKEN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_USBOTG_BUSCLKEN_OFFSET 20
#define BUS_CLK_GATING0_REG_USBOTG_BUSCLKEN_CLEAR_MASK (0x00100000)
#define BUS_CLK_GATING0_REG_USBOTG_BUSCLKEN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_USBOTG_BUSCLKEN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_USB_HCLK_EN_OFFSET 19
#define BUS_CLK_GATING0_REG_USB_HCLK_EN_CLEAR_MASK (0x00080000)
#define BUS_CLK_GATING0_REG_USB_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_USB_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_UART3_PCLK_EN_OFFSET 18
#define BUS_CLK_GATING0_REG_UART3_PCLK_EN_CLEAR_MASK (0x00040000)
#define BUS_CLK_GATING0_REG_UART3_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_UART3_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_UART2_PCLK_EN_OFFSET 17
#define BUS_CLK_GATING0_REG_UART2_PCLK_EN_CLEAR_MASK (0x00020000)
#define BUS_CLK_GATING0_REG_UART2_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_UART2_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_UART1_PCLK_EN_OFFSET 16
#define BUS_CLK_GATING0_REG_UART1_PCLK_EN_CLEAR_MASK (0x00010000)
#define BUS_CLK_GATING0_REG_UART1_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_UART1_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_UART0_PCLK_EN_OFFSET 15
#define BUS_CLK_GATING0_REG_UART0_PCLK_EN_CLEAR_MASK (0x00008000)
#define BUS_CLK_GATING0_REG_UART0_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_UART0_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_TWI0_PCLK_EN_OFFSET 14
#define BUS_CLK_GATING0_REG_TWI0_PCLK_EN_CLEAR_MASK (0x00004000)
#define BUS_CLK_GATING0_REG_TWI0_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_TWI0_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_PWM_PCLK_EN_OFFSET 13
#define BUS_CLK_GATING0_REG_PWM_PCLK_EN_CLEAR_MASK (0x00002000)
#define BUS_CLK_GATING0_REG_PWM_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_PWM_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_WG_PCLK_EN_OFFSET 12
#define BUS_CLK_GATING0_REG_WG_PCLK_EN_CLEAR_MASK (0x00001000)
#define BUS_CLK_GATING0_REG_WG_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_WG_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_TRNG_PCLK_EN_OFFSET 11
#define BUS_CLK_GATING0_REG_TRNG_PCLK_EN_CLEAR_MASK (0x00000800)
#define BUS_CLK_GATING0_REG_TRNG_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_TRNG_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_TIMER_PCLK_EN_OFFSET 10
#define BUS_CLK_GATING0_REG_TIMER_PCLK_EN_CLEAR_MASK (0x00000400)
#define BUS_CLK_GATING0_REG_TIMER_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_TIMER_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_SGDMA_HCLK_EN_OFFSET 9
#define BUS_CLK_GATING0_REG_SGDMA_HCLK_EN_CLEAR_MASK (0x00000200)
#define BUS_CLK_GATING0_REG_SGDMA_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_SGDMA_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_DMA_HCLK_EN_OFFSET 8
#define BUS_CLK_GATING0_REG_DMA_HCLK_EN_CLEAR_MASK (0x00000100)
#define BUS_CLK_GATING0_REG_DMA_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_DMA_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_SYSCTRL_HCLK_EN_OFFSET 7
#define BUS_CLK_GATING0_REG_SYSCTRL_HCLK_EN_CLEAR_MASK (0x00000080)
#define BUS_CLK_GATING0_REG_SYSCTRL_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_SYSCTRL_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_CE_HCLK_EN_OFFSET 6
#define BUS_CLK_GATING0_REG_CE_HCLK_EN_CLEAR_MASK (0x00000040)
#define BUS_CLK_GATING0_REG_CE_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_CE_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_HSTIMER_HCLKEN_OFFSET 5
#define BUS_CLK_GATING0_REG_HSTIMER_HCLKEN_CLEAR_MASK (0x00000020)
#define BUS_CLK_GATING0_REG_HSTIMER_HCLKEN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_HSTIMER_HCLKEN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_SPLOCK_HCLKEN_OFFSET 4
#define BUS_CLK_GATING0_REG_SPLOCK_HCLKEN_CLEAR_MASK (0x00000010)
#define BUS_CLK_GATING0_REG_SPLOCK_HCLKEN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_SPLOCK_HCLKEN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_DRAM_GATING_OFFSET 3
#define BUS_CLK_GATING0_REG_DRAM_GATING_CLEAR_MASK (0x00000008)
#define BUS_CLK_GATING0_REG_DRAM_GATING_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_DRAM_GATING_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_RV_MSGBOX_HCLKEN_OFFSET 2
#define BUS_CLK_GATING0_REG_RV_MSGBOX_HCLKEN_CLEAR_MASK (0x00000004)
#define BUS_CLK_GATING0_REG_RV_MSGBOX_HCLKEN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_RV_MSGBOX_HCLKEN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING0_REG_RISCV_CFG_CLKEN_OFFSET 0
#define BUS_CLK_GATING0_REG_RISCV_CFG_CLKEN_CLEAR_MASK (0x00000001)
#define BUS_CLK_GATING0_REG_RISCV_CFG_CLKEN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING0_REG_RISCV_CFG_CLKEN_CLOCK_IS_ON 0b1

#define BUS_CLK_GATING1_REG 0x00000084//CCU_APP Bus CLK Gating1 Register
#define BUS_CLK_GATING1_REG_G2D_MBUS_CLK_EN_OFFSET 31
#define BUS_CLK_GATING1_REG_G2D_MBUS_CLK_EN_CLEAR_MASK (0x80000000)
#define BUS_CLK_GATING1_REG_G2D_MBUS_CLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_G2D_MBUS_CLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_G2D_CLK_EN_OFFSET 30
#define BUS_CLK_GATING1_REG_G2D_CLK_EN_CLEAR_MASK (0x40000000)
#define BUS_CLK_GATING1_REG_G2D_CLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_G2D_CLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_G2D_HB_CLK_EN_OFFSET 29
#define BUS_CLK_GATING1_REG_G2D_HB_CLK_EN_CLEAR_MASK (0x20000000)
#define BUS_CLK_GATING1_REG_G2D_HB_CLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_G2D_HB_CLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_MCSI_HCLK_EN_OFFSET 28
#define BUS_CLK_GATING1_REG_MCSI_HCLK_EN_CLEAR_MASK (0x10000000)
#define BUS_CLK_GATING1_REG_MCSI_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_MCSI_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_MCSI_SCLK_EN_OFFSET 27
#define BUS_CLK_GATING1_REG_MCSI_SCLK_EN_CLEAR_MASK (0x08000000)
#define BUS_CLK_GATING1_REG_MCSI_SCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_MCSI_SCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_MISP_SCLK_EN_OFFSET 26
#define BUS_CLK_GATING1_REG_MISP_SCLK_EN_CLEAR_MASK (0x04000000)
#define BUS_CLK_GATING1_REG_MISP_SCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_MISP_SCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_TWI2_PCLK_EN_OFFSET 25
#define BUS_CLK_GATING1_REG_TWI2_PCLK_EN_CLEAR_MASK (0x02000000)
#define BUS_CLK_GATING1_REG_TWI2_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_TWI2_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_TWI1_PCLK_EN_OFFSET 24
#define BUS_CLK_GATING1_REG_TWI1_PCLK_EN_CLEAR_MASK (0x01000000)
#define BUS_CLK_GATING1_REG_TWI1_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_TWI1_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_SPI2_HCLK_EN_OFFSET 23
#define BUS_CLK_GATING1_REG_SPI2_HCLK_EN_CLEAR_MASK (0x00800000)
#define BUS_CLK_GATING1_REG_SPI2_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_SPI2_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_GMAC_HBUS_EN_OFFSET 22
#define BUS_CLK_GATING1_REG_GMAC_HBUS_EN_CLEAR_MASK (0x00400000)
#define BUS_CLK_GATING1_REG_GMAC_HBUS_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_GMAC_HBUS_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_SMHC1_HCLK_EN_OFFSET 21
#define BUS_CLK_GATING1_REG_SMHC1_HCLK_EN_CLEAR_MASK (0x00200000)
#define BUS_CLK_GATING1_REG_SMHC1_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_SMHC1_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_SMHC0_HCLK_EN_OFFSET 20
#define BUS_CLK_GATING1_REG_SMHC0_HCLK_EN_CLEAR_MASK (0x00100000)
#define BUS_CLK_GATING1_REG_SMHC0_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_SMHC0_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_SPI1_HCLK_EN_OFFSET 19
#define BUS_CLK_GATING1_REG_SPI1_HCLK_EN_CLEAR_MASK (0x00080000)
#define BUS_CLK_GATING1_REG_SPI1_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_SPI1_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_DBGSYS_BUSCLKEN_OFFSET 18
#define BUS_CLK_GATING1_REG_DBGSYS_BUSCLKEN_CLEAR_MASK (0x00040000)
#define BUS_CLK_GATING1_REG_DBGSYS_BUSCLKEN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_DBGSYS_BUSCLKEN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_GMAC_MBUS_AHB_GATE_SW_OFFSET 17
#define BUS_CLK_GATING1_REG_GMAC_MBUS_AHB_GATE_SW_CLEAR_MASK (0x00020000)
#define BUS_CLK_GATING1_REG_GMAC_MBUS_AHB_GATE_SW_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_GMAC_MBUS_AHB_GATE_SW_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_SMHC1_MBUS_AHB_GATE_SW_OFFSET 16
#define BUS_CLK_GATING1_REG_SMHC1_MBUS_AHB_GATE_SW_CLEAR_MASK (0x00010000)
#define BUS_CLK_GATING1_REG_SMHC1_MBUS_AHB_GATE_SW_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_SMHC1_MBUS_AHB_GATE_SW_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_SMHC0_MBUS_AHB_GATE_SW_OFFSET 15
#define BUS_CLK_GATING1_REG_SMHC0_MBUS_AHB_GATE_SW_CLEAR_MASK (0x00008000)
#define BUS_CLK_GATING1_REG_SMHC0_MBUS_AHB_GATE_SW_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_SMHC0_MBUS_AHB_GATE_SW_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_USB_MBUS_AHB_GATE_SW_OFFSET 14
#define BUS_CLK_GATING1_REG_USB_MBUS_AHB_GATE_SW_CLEAR_MASK (0x00004000)
#define BUS_CLK_GATING1_REG_USB_MBUS_AHB_GATE_SW_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_USB_MBUS_AHB_GATE_SW_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_DMA_MBUS_GATE_SW_OFFSET 13
#define BUS_CLK_GATING1_REG_DMA_MBUS_GATE_SW_CLEAR_MASK (0x00002000)
#define BUS_CLK_GATING1_REG_DMA_MBUS_GATE_SW_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_DMA_MBUS_GATE_SW_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_MBUS_GATE_SW_OFFSET 12
#define BUS_CLK_GATING1_REG_MBUS_GATE_SW_CLEAR_MASK (0x00001000)
#define BUS_CLK_GATING1_REG_MBUS_GATE_SW_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_MBUS_GATE_SW_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_I2S1_PCLK_EN_OFFSET 9
#define BUS_CLK_GATING1_REG_I2S1_PCLK_EN_CLEAR_MASK (0x00000200)
#define BUS_CLK_GATING1_REG_I2S1_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_I2S1_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_I2S0_PCLK_EN_OFFSET 8
#define BUS_CLK_GATING1_REG_I2S0_PCLK_EN_CLEAR_MASK (0x00000100)
#define BUS_CLK_GATING1_REG_I2S0_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_I2S0_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_DMIC_PCLK_EN_OFFSET 7
#define BUS_CLK_GATING1_REG_DMIC_PCLK_EN_CLEAR_MASK (0x00000080)
#define BUS_CLK_GATING1_REG_DMIC_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_DMIC_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_ADDA_PCLK_EN_OFFSET 6
#define BUS_CLK_GATING1_REG_ADDA_PCLK_EN_CLEAR_MASK (0x00000040)
#define BUS_CLK_GATING1_REG_ADDA_PCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_ADDA_PCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_SPIF_HCLK_EN_OFFSET 5
#define BUS_CLK_GATING1_REG_SPIF_HCLK_EN_CLEAR_MASK (0x00000020)
#define BUS_CLK_GATING1_REG_SPIF_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_SPIF_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_SPI_HCLK_EN_OFFSET 4
#define BUS_CLK_GATING1_REG_SPI_HCLK_EN_CLEAR_MASK (0x00000010)
#define BUS_CLK_GATING1_REG_SPI_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_SPI_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_VE_AHB_CLK_EN_OFFSET 3
#define BUS_CLK_GATING1_REG_VE_AHB_CLK_EN_CLEAR_MASK (0x00000008)
#define BUS_CLK_GATING1_REG_VE_AHB_CLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_VE_AHB_CLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_VE_MBUS_CLK_EN_OFFSET 2
#define BUS_CLK_GATING1_REG_VE_MBUS_CLK_EN_CLEAR_MASK (0x00000004)
#define BUS_CLK_GATING1_REG_VE_MBUS_CLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING1_REG_VE_MBUS_CLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING1_REG_THS_PCLK_GATING_OFFSET 1
#define BUS_CLK_GATING1_REG_THS_PCLK_GATING_CLEAR_MASK (0x00000002)
#define BUS_CLK_GATING1_REG_THS_PCLK_GATING_MASK 0b0
#define BUS_CLK_GATING1_REG_THS_PCLK_GATING_PASS 0b1
#define BUS_CLK_GATING1_REG_GPA_PCLK_GATING_OFFSET 0
#define BUS_CLK_GATING1_REG_GPA_PCLK_GATING_CLEAR_MASK (0x00000001)
#define BUS_CLK_GATING1_REG_GPA_PCLK_GATING_MASK 0b0
#define BUS_CLK_GATING1_REG_GPA_PCLK_GATING_PASS 0b1

#define BUS_CLK_GATING2_REG 0x00000088//CCU_APP Bus CLK Gating2 Register
#define BUS_CLK_GATING2_REG_MCSI_HCLK_EN_OFFSET 28
#define BUS_CLK_GATING2_REG_MCSI_HCLK_EN_CLEAR_MASK (0x10000000)
#define BUS_CLK_GATING2_REG_MCSI_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_MCSI_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING2_REG_MCSI_SCLK_EN_OFFSET 27
#define BUS_CLK_GATING2_REG_MCSI_SCLK_EN_CLEAR_MASK (0x08000000)
#define BUS_CLK_GATING2_REG_MCSI_SCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_MCSI_SCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING2_REG_MISP_SCLK_EN_OFFSET 26
#define BUS_CLK_GATING2_REG_MISP_SCLK_EN_CLEAR_MASK (0x04000000)
#define BUS_CLK_GATING2_REG_MISP_SCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_MISP_SCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING2_REG_RES_DCAP_24M_EN_OFFSET 10
#define BUS_CLK_GATING2_REG_RES_DCAP_24M_EN_CLEAR_MASK (0x00000400)
#define BUS_CLK_GATING2_REG_RES_DCAP_24M_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_RES_DCAP_24M_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING2_REG_SD_MONITOR_EN_OFFSET 9
#define BUS_CLK_GATING2_REG_SD_MONITOR_EN_CLEAR_MASK (0x00000200)
#define BUS_CLK_GATING2_REG_SD_MONITOR_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_SD_MONITOR_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING2_REG_AHB_MONITOR_EN_OFFSET 8
#define BUS_CLK_GATING2_REG_AHB_MONITOR_EN_CLEAR_MASK (0x00000100)
#define BUS_CLK_GATING2_REG_AHB_MONITOR_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_AHB_MONITOR_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING2_REG_VE_SCLK_EN_OFFSET 5
#define BUS_CLK_GATING2_REG_VE_SCLK_EN_CLEAR_MASK (0x00000020)
#define BUS_CLK_GATING2_REG_VE_SCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_VE_SCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING2_REG_VE_HCLK_EN_OFFSET 4
#define BUS_CLK_GATING2_REG_VE_HCLK_EN_CLEAR_MASK (0x00000010)
#define BUS_CLK_GATING2_REG_VE_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_VE_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING2_REG_TCON_HCLK_EN_OFFSET 3
#define BUS_CLK_GATING2_REG_TCON_HCLK_EN_CLEAR_MASK (0x00000008)
#define BUS_CLK_GATING2_REG_TCON_HCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_TCON_HCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING2_REG_SGDMA_MCLK_EN_OFFSET 2
#define BUS_CLK_GATING2_REG_SGDMA_MCLK_EN_CLEAR_MASK (0x00000004)
#define BUS_CLK_GATING2_REG_SGDMA_MCLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_SGDMA_MCLK_EN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING2_REG_DE_CLKEN_OFFSET 1
#define BUS_CLK_GATING2_REG_DE_CLKEN_CLEAR_MASK (0x00000002)
#define BUS_CLK_GATING2_REG_DE_CLKEN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_DE_CLKEN_CLOCK_IS_ON 0b1
#define BUS_CLK_GATING2_REG_DE_HB_CLK_EN_OFFSET 0
#define BUS_CLK_GATING2_REG_DE_HB_CLK_EN_CLEAR_MASK (0x00000001)
#define BUS_CLK_GATING2_REG_DE_HB_CLK_EN_CLOCK_IS_OFF 0b0
#define BUS_CLK_GATING2_REG_DE_HB_CLK_EN_CLOCK_IS_ON 0b1

#define BUS_Reset0_REG 0x00000090//CCU_APP Bus Reset0 Register
#define BUS_Reset0_REG_DPSS_TOP_RSTN_SW_OFFSET 31
#define BUS_Reset0_REG_DPSS_TOP_RSTN_SW_CLEAR_MASK (0x80000000)
#define BUS_Reset0_REG_DPSS_TOP_RSTN_SW_ASSERT 0b0
#define BUS_Reset0_REG_DPSS_TOP_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_WKUP_TMR_RSTN_SW_OFFSET 29
#define BUS_Reset0_REG_WKUP_TMR_RSTN_SW_CLEAR_MASK (0x20000000)
#define BUS_Reset0_REG_WKUP_TMR_RSTN_SW_ASSERT 0b0
#define BUS_Reset0_REG_WKUP_TMR_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_MCSI_RSTN_SW_OFFSET 28
#define BUS_Reset0_REG_MCSI_RSTN_SW_CLEAR_MASK (0x10000000)
#define BUS_Reset0_REG_MCSI_RSTN_SW_ASSERT 0b0
#define BUS_Reset0_REG_MCSI_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_MCSI_SW_OFFSET 27
#define BUS_Reset0_REG_HRESETN_MCSI_SW_CLEAR_MASK (0x08000000)
#define BUS_Reset0_REG_HRESETN_MCSI_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_MCSI_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_G2D_SW_OFFSET 26
#define BUS_Reset0_REG_HRESETN_G2D_SW_CLEAR_MASK (0x04000000)
#define BUS_Reset0_REG_HRESETN_G2D_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_G2D_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_DE_SW_OFFSET 25
#define BUS_Reset0_REG_HRESETN_DE_SW_CLEAR_MASK (0x02000000)
#define BUS_Reset0_REG_HRESETN_DE_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_DE_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_GMAC_SW_OFFSET 24
#define BUS_Reset0_REG_HRESETN_GMAC_SW_CLEAR_MASK (0x01000000)
#define BUS_Reset0_REG_HRESETN_GMAC_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_GMAC_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_USB_PHY_SW_OFFSET 23
#define BUS_Reset0_REG_HRESETN_USB_PHY_SW_CLEAR_MASK (0x00800000)
#define BUS_Reset0_REG_HRESETN_USB_PHY_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_USB_PHY_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_USB_OHCI_SW_OFFSET 22
#define BUS_Reset0_REG_HRESETN_USB_OHCI_SW_CLEAR_MASK (0x00400000)
#define BUS_Reset0_REG_HRESETN_USB_OHCI_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_USB_OHCI_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_USB_EHCI_SW_OFFSET 21
#define BUS_Reset0_REG_HRESETN_USB_EHCI_SW_CLEAR_MASK (0x00200000)
#define BUS_Reset0_REG_HRESETN_USB_EHCI_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_USB_EHCI_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_USB_OTG_SW_OFFSET 20
#define BUS_Reset0_REG_HRESETN_USB_OTG_SW_CLEAR_MASK (0x00100000)
#define BUS_Reset0_REG_HRESETN_USB_OTG_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_USB_OTG_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_USB_SW_OFFSET 19
#define BUS_Reset0_REG_HRESETN_USB_SW_CLEAR_MASK (0x00080000)
#define BUS_Reset0_REG_HRESETN_USB_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_USB_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_PRESETN_UART3_SW_OFFSET 18
#define BUS_Reset0_REG_PRESETN_UART3_SW_CLEAR_MASK (0x00040000)
#define BUS_Reset0_REG_PRESETN_UART3_SW_ASSERT 0b0
#define BUS_Reset0_REG_PRESETN_UART3_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_PRESETN_UART2_SW_OFFSET 17
#define BUS_Reset0_REG_PRESETN_UART2_SW_CLEAR_MASK (0x00020000)
#define BUS_Reset0_REG_PRESETN_UART2_SW_ASSERT 0b0
#define BUS_Reset0_REG_PRESETN_UART2_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_PRESETN_UART1_SW_OFFSET 16
#define BUS_Reset0_REG_PRESETN_UART1_SW_CLEAR_MASK (0x00010000)
#define BUS_Reset0_REG_PRESETN_UART1_SW_ASSERT 0b0
#define BUS_Reset0_REG_PRESETN_UART1_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_PRESETN_UART0_SW_OFFSET 15
#define BUS_Reset0_REG_PRESETN_UART0_SW_CLEAR_MASK (0x00008000)
#define BUS_Reset0_REG_PRESETN_UART0_SW_ASSERT 0b0
#define BUS_Reset0_REG_PRESETN_UART0_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_PRESETN_TWI0_SW_OFFSET 14
#define BUS_Reset0_REG_PRESETN_TWI0_SW_CLEAR_MASK (0x00004000)
#define BUS_Reset0_REG_PRESETN_TWI0_SW_ASSERT 0b0
#define BUS_Reset0_REG_PRESETN_TWI0_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_PRESETN_PWM_SW_OFFSET 13
#define BUS_Reset0_REG_PRESETN_PWM_SW_CLEAR_MASK (0x00002000)
#define BUS_Reset0_REG_PRESETN_PWM_SW_ASSERT 0b0
#define BUS_Reset0_REG_PRESETN_PWM_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_PRESETN_WIEGAND_SW_OFFSET 12
#define BUS_Reset0_REG_PRESETN_WIEGAND_SW_CLEAR_MASK (0x00001000)
#define BUS_Reset0_REG_PRESETN_WIEGAND_SW_ASSERT 0b0
#define BUS_Reset0_REG_PRESETN_WIEGAND_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_PRESETN_TRNG_SW_OFFSET 11
#define BUS_Reset0_REG_PRESETN_TRNG_SW_CLEAR_MASK (0x00000800)
#define BUS_Reset0_REG_PRESETN_TRNG_SW_ASSERT 0b0
#define BUS_Reset0_REG_PRESETN_TRNG_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_PRESETN_TIMER_SW_OFFSET 10
#define BUS_Reset0_REG_PRESETN_TIMER_SW_CLEAR_MASK (0x00000400)
#define BUS_Reset0_REG_PRESETN_TIMER_SW_ASSERT 0b0
#define BUS_Reset0_REG_PRESETN_TIMER_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_SGDMA_SW_OFFSET 9
#define BUS_Reset0_REG_HRESETN_SGDMA_SW_CLEAR_MASK (0x00000200)
#define BUS_Reset0_REG_HRESETN_SGDMA_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_SGDMA_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_DMA_SW_OFFSET 8
#define BUS_Reset0_REG_HRESETN_DMA_SW_CLEAR_MASK (0x00000100)
#define BUS_Reset0_REG_HRESETN_DMA_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_DMA_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_SYSCTRL_SW_OFFSET 7
#define BUS_Reset0_REG_HRESETN_SYSCTRL_SW_CLEAR_MASK (0x00000080)
#define BUS_Reset0_REG_HRESETN_SYSCTRL_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_SYSCTRL_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_CE_SW_OFFSET 6
#define BUS_Reset0_REG_HRESETN_CE_SW_CLEAR_MASK (0x00000040)
#define BUS_Reset0_REG_HRESETN_CE_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_CE_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_HSTIMER_SW_OFFSET 5
#define BUS_Reset0_REG_HRESETN_HSTIMER_SW_CLEAR_MASK (0x00000020)
#define BUS_Reset0_REG_HRESETN_HSTIMER_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_HSTIMER_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_HRESETN_SPLOCK_SW_OFFSET 4
#define BUS_Reset0_REG_HRESETN_SPLOCK_SW_CLEAR_MASK (0x00000010)
#define BUS_Reset0_REG_HRESETN_SPLOCK_SW_ASSERT 0b0
#define BUS_Reset0_REG_HRESETN_SPLOCK_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_DRAM_OFFSET 3
#define BUS_Reset0_REG_DRAM_CLEAR_MASK (0x00000008)
#define BUS_Reset0_REG_DRAM_ASSERT 0b0
#define BUS_Reset0_REG_DRAM_DE_ASSERT 0b1
#define BUS_Reset0_REG_RV_MSGBOX_RSTN_SW_OFFSET 2
#define BUS_Reset0_REG_RV_MSGBOX_RSTN_SW_CLEAR_MASK (0x00000004)
#define BUS_Reset0_REG_RV_MSGBOX_RSTN_SW_ASSERT 0b0
#define BUS_Reset0_REG_RV_MSGBOX_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_RV_SYS_APB_RSTN_SW_OFFSET 1
#define BUS_Reset0_REG_RV_SYS_APB_RSTN_SW_CLEAR_MASK (0x00000002)
#define BUS_Reset0_REG_RV_SYS_APB_RSTN_SW_ASSERT 0b0
#define BUS_Reset0_REG_RV_SYS_APB_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset0_REG_RV_CFG_RSTN_SW_OFFSET 0
#define BUS_Reset0_REG_RV_CFG_RSTN_SW_CLEAR_MASK (0x00000001)
#define BUS_Reset0_REG_RV_CFG_RSTN_SW_ASSERT 0b0
#define BUS_Reset0_REG_RV_CFG_RSTN_SW_DE_ASSERT 0b1

#define BUS_Reset1_REG 0x00000094//CCU_APP Bus Reset1 Register
#define BUS_Reset1_REG_A27_CFG_RSTN_SW_OFFSET 28
#define BUS_Reset1_REG_A27_CFG_RSTN_SW_CLEAR_MASK (0x10000000)
#define BUS_Reset1_REG_A27_CFG_RSTN_SW_ASSERT 0b0
#define BUS_Reset1_REG_A27_CFG_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_A27_MSGBOX_RSTN_SW_OFFSET 27
#define BUS_Reset1_REG_A27_MSGBOX_RSTN_SW_CLEAR_MASK (0x08000000)
#define BUS_Reset1_REG_A27_MSGBOX_RSTN_SW_ASSERT 0b0
#define BUS_Reset1_REG_A27_MSGBOX_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_A27_RSTN_SW_OFFSET 26
#define BUS_Reset1_REG_A27_RSTN_SW_CLEAR_MASK (0x04000000)
#define BUS_Reset1_REG_A27_RSTN_SW_ASSERT 0b0
#define BUS_Reset1_REG_A27_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_PRESETN_TWI2_SW_OFFSET 25
#define BUS_Reset1_REG_PRESETN_TWI2_SW_CLEAR_MASK (0x02000000)
#define BUS_Reset1_REG_PRESETN_TWI2_SW_ASSERT 0b0
#define BUS_Reset1_REG_PRESETN_TWI2_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_PRESETN_TWI1_SW_OFFSET 24
#define BUS_Reset1_REG_PRESETN_TWI1_SW_CLEAR_MASK (0x01000000)
#define BUS_Reset1_REG_PRESETN_TWI1_SW_ASSERT 0b0
#define BUS_Reset1_REG_PRESETN_TWI1_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_HRESETN_SPI2_SW_OFFSET 23
#define BUS_Reset1_REG_HRESETN_SPI2_SW_CLEAR_MASK (0x00800000)
#define BUS_Reset1_REG_HRESETN_SPI2_SW_ASSERT 0b0
#define BUS_Reset1_REG_HRESETN_SPI2_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_HRESETN_SMHC1_SW_OFFSET 21
#define BUS_Reset1_REG_HRESETN_SMHC1_SW_CLEAR_MASK (0x00200000)
#define BUS_Reset1_REG_HRESETN_SMHC1_SW_ASSERT 0b0
#define BUS_Reset1_REG_HRESETN_SMHC1_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_HRESETN_SMHC0_SW_OFFSET 20
#define BUS_Reset1_REG_HRESETN_SMHC0_SW_CLEAR_MASK (0x00100000)
#define BUS_Reset1_REG_HRESETN_SMHC0_SW_ASSERT 0b0
#define BUS_Reset1_REG_HRESETN_SMHC0_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_HRESETN_SPI1_SW_OFFSET 19
#define BUS_Reset1_REG_HRESETN_SPI1_SW_CLEAR_MASK (0x00080000)
#define BUS_Reset1_REG_HRESETN_SPI1_SW_ASSERT 0b0
#define BUS_Reset1_REG_HRESETN_SPI1_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_DBGSYS_RSTN_SW_OFFSET 18
#define BUS_Reset1_REG_DBGSYS_RSTN_SW_CLEAR_MASK (0x00040000)
#define BUS_Reset1_REG_DBGSYS_RSTN_SW_ASSERT 0b0
#define BUS_Reset1_REG_DBGSYS_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_MBUS_RSTN_SW_OFFSET 12
#define BUS_Reset1_REG_MBUS_RSTN_SW_CLEAR_MASK (0x00001000)
#define BUS_Reset1_REG_MBUS_RSTN_SW_ASSERT 0b0
#define BUS_Reset1_REG_MBUS_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_TCON_LCD_RSTN_SW_OFFSET 11
#define BUS_Reset1_REG_TCON_LCD_RSTN_SW_CLEAR_MASK (0x00000800)
#define BUS_Reset1_REG_TCON_LCD_RSTN_SW_ASSERT 0b0
#define BUS_Reset1_REG_TCON_LCD_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_VO0_HRESETN_SW_OFFSET 10
#define BUS_Reset1_REG_VO0_HRESETN_SW_CLEAR_MASK (0x00000400)
#define BUS_Reset1_REG_VO0_HRESETN_SW_ASSERT 0b0
#define BUS_Reset1_REG_VO0_HRESETN_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_HRESETN_I2S1_SW_OFFSET 9
#define BUS_Reset1_REG_HRESETN_I2S1_SW_CLEAR_MASK (0x00000200)
#define BUS_Reset1_REG_HRESETN_I2S1_SW_ASSERT 0b0
#define BUS_Reset1_REG_HRESETN_I2S1_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_HRESETN_I2S0_SW_OFFSET 8
#define BUS_Reset1_REG_HRESETN_I2S0_SW_CLEAR_MASK (0x00000100)
#define BUS_Reset1_REG_HRESETN_I2S0_SW_ASSERT 0b0
#define BUS_Reset1_REG_HRESETN_I2S0_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_HRESETN_DMIC_SW_OFFSET 7
#define BUS_Reset1_REG_HRESETN_DMIC_SW_CLEAR_MASK (0x00000080)
#define BUS_Reset1_REG_HRESETN_DMIC_SW_ASSERT 0b0
#define BUS_Reset1_REG_HRESETN_DMIC_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_HRESETN_AUDIO_SW_OFFSET 6
#define BUS_Reset1_REG_HRESETN_AUDIO_SW_CLEAR_MASK (0x00000040)
#define BUS_Reset1_REG_HRESETN_AUDIO_SW_ASSERT 0b0
#define BUS_Reset1_REG_HRESETN_AUDIO_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_HRESETN_SPIF_SW_OFFSET 5
#define BUS_Reset1_REG_HRESETN_SPIF_SW_CLEAR_MASK (0x00000020)
#define BUS_Reset1_REG_HRESETN_SPIF_SW_ASSERT 0b0
#define BUS_Reset1_REG_HRESETN_SPIF_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_HRESETN_SPI_SW_OFFSET 4
#define BUS_Reset1_REG_HRESETN_SPI_SW_CLEAR_MASK (0x00000010)
#define BUS_Reset1_REG_HRESETN_SPI_SW_ASSERT 0b0
#define BUS_Reset1_REG_HRESETN_SPI_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_VE_RSTN_SW_OFFSET 3
#define BUS_Reset1_REG_VE_RSTN_SW_CLEAR_MASK (0x00000008)
#define BUS_Reset1_REG_VE_RSTN_SW_ASSERT 0b0
#define BUS_Reset1_REG_VE_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_THS_RSTN_SW_OFFSET 1
#define BUS_Reset1_REG_THS_RSTN_SW_CLEAR_MASK (0x00000002)
#define BUS_Reset1_REG_THS_RSTN_SW_ASSERT 0b0
#define BUS_Reset1_REG_THS_RSTN_SW_DE_ASSERT 0b1
#define BUS_Reset1_REG_GPA_RSTN_SW_OFFSET 0
#define BUS_Reset1_REG_GPA_RSTN_SW_CLEAR_MASK (0x00000001)
#define BUS_Reset1_REG_GPA_RSTN_SW_ASSERT 0b0
#define BUS_Reset1_REG_GPA_RSTN_SW_DE_ASSERT 0b1

#define RV_WDG_Reset_REG 0x00000098//RV_WDG_Reset Register
#define RV_WDG_Reset_REG_A27_WFG_RSTN_SW_OFFSET 2
#define RV_WDG_Reset_REG_A27_WFG_RSTN_SW_CLEAR_MASK (0x00000004)
#define RV_WDG_Reset_REG_A27_WFG_RSTN_SW_ASSERT 0b0
#define RV_WDG_Reset_REG_A27_WFG_RSTN_SW_DE_ASSERT 0b1
#define RV_WDG_Reset_REG_GPIO_WDG_RSTN_OFFSET 1
#define RV_WDG_Reset_REG_GPIO_WDG_RSTN_CLEAR_MASK (0x00000002)
#define RV_WDG_Reset_REG_GPIO_WDG_RSTN_WDG_CAN_RESET_GPIO 0b0
#define RV_WDG_Reset_REG_GPIO_WDG_RSTN_WDG_CAN_NOT_RESET_GPIO 0b1
#define RV_WDG_Reset_REG_RV_WDG_RSTN_SW_OFFSET 0
#define RV_WDG_Reset_REG_RV_WDG_RSTN_SW_CLEAR_MASK (0x00000001)
#define RV_WDG_Reset_REG_RV_WDG_RSTN_SW_ASSERT 0b0
#define RV_WDG_Reset_REG_RV_WDG_RSTN_SW_DE_ASSERT 0b1

#define E907_RSTN_REG 0x0000009c//E907_Reset Register
#define E907_RSTN_REG_E907_RSTN_SW_WRITE_LOCK_OFFSET 16
#define E907_RSTN_REG_E907_RSTN_SW_WRITE_LOCK_CLEAR_MASK (0xffff0000)
#define E907_RSTN_REG_E907_RSTN_SW_OFFSET 0
#define E907_RSTN_REG_E907_RSTN_SW_CLEAR_MASK (0x00000001)
#define E907_RSTN_REG_E907_RSTN_SW_ASSERT 0b0
#define E907_RSTN_REG_E907_RSTN_SW_DE_ASSERT 0b1

#define SUNXI_CCM_AON_BASE SUNXI_CCU_AON_BASE
/* pll list */

#define CCU_PLL_PERI0_CTRL_REG (SUNXI_CCM_AON_BASE + PLL_PERI_CTRL0_REG)
#define CCU_PLL_PERI1_CTRL_REG (SUNXI_CCM_AON_BASE + PLL_PERI_CTRL1_REG)
#define CCU_PLL_DDR0_CTRL_REG (SUNXI_CCM_AON_BASE + PLL_DDR_CTRL_REG)
#define CCU_PLL_PERI_PAT0_CTRL_REG (SUNXI_CCM_AON_BASE + PLL_PERI_PAT0_CTRL_REG)
#define CCU_PLL_PERI_PAT1_CTRL_REG (SUNXI_CCM_AON_BASE + PLL_PERI_PAT1_CTRL_REG)
#define CCU_PLL_DDR_PAT0_CTRL_REG (SUNXI_CCM_AON_BASE + PLL_DDR_PAT0_CTRL_REG)
#define CCU_PLL_DDR_PAT1_CTRL_REG (SUNXI_CCM_AON_BASE + PLL_DDR_PAT1_CTRL_REG)
#define CCU_PLL_CPU_BIAS_REG (SUNXI_CCM_AON_BASE + PLL_CPU_BIAS_REG)
#define CCU_PLL_PERI_BIAS_REG (SUNXI_CCM_AON_BASE + PLL_PERI_BIAS_REG)
#define CCU_PLL_DDR_BIAS_REG (SUNXI_CCM_AON_BASE + PLL_DDR_BIAS_REG)
#define CCU_PLL_CPU_TUN_REG (SUNXI_CCM_AON_BASE + PLL_CPU_TUN_REG)
#define CCU_PLL_FUNC_CFG_REG (SUNXI_CCM_AON_BASE + PLL_FUNC_CFG_REG)

#define CCU_PLL_CPUX_CTRL_REG (SUNXI_CCM_AON_BASE + PLL_CPU_CTRL_REG)
#define CCU_AON_PLL_CPU_D_1 (0)
#define CCU_AON_PLL_CPU_D_2 (1)
#define CCU_AON_PLL_CPU_D_4 (3)
#define CCU_AON_PLL_CPU_M_1 (0)
#define CCU_AON_PLL_CPU_M_2 (1)
#define CCU_AON_PLL_CPU_M_3 (2)
#define CCU_AON_PLL_CPU_M_4 (3)
#define CCU_AON_PLL_CPU_M_5 (4)
#define CCU_AON_PLL_CPU_N_24 (23)
#define CCU_AON_PLL_CPU_N_25 (24)
#define CCU_AON_PLL_CPU_N_27 (26)
#define CCU_AON_PLL_CPU_N_30 (29)
#define CCU_AON_PLL_CPU_N_40 (39)
#define CCU_AON_PLL_CPU_N_41 (40)
#define CCU_AON_PLL_CPU_N_45 (44)
#define CCU_AON_PLL_CPU_N_50 (49)
#define CCU_AON_PLL_CPU_N_56 (55)
#define CCU_AON_PLL_CPU_N_67 (66)
#define CCU_AON_PLL_CPU_N_96 (95)
#define CCU_AON_PLL_CPU_N_99 (98)
#define CCU_AON_PLL_CPU_N_118 (117)
#define CCU_AON_PLL_CPU_N_192 (191)

#define CCU_PLL_PERI_CTRL0_REG (SUNXI_CCM_AON_BASE + PLL_PERI_CTRL0_REG)
#define CCU_PLL_PERI_CTRL1_REG (SUNXI_CCM_AON_BASE + PLL_PERI_CTRL1_REG)
#define CCU_PLL_VIDEO_CTRL_REG (SUNXI_CCM_AON_BASE + PLL_VIDEO_CTRL_REG)
#define CCU_PLL_CSI_CTRL_REG (SUNXI_CCM_AON_BASE + PLL_CSI_CTRL_REG)
#define CCU_PLL_CSI_PAT0_REG (SUNXI_CCM_AON_BASE + PLL_CSI_PAT0_CTRL_REG)
#define CCU_PLL_CSI_PAT1_REG (SUNXI_CCM_AON_BASE + PLL_CSI_PAT1_CTRL_REG)

#define CCU_AHB_CLK_REG (SUNXI_CCM_AON_BASE + AHB_CLK_REG)
#define CCU_APB_CLK_REG (SUNXI_CCM_AON_BASE + APB_CLK_REG)
#define CCU_APB_SPEC_CLK_REG (SUNXI_CCM_AON_BASE + APB_SPEC_CLK_REG)

#define CCU_E90X_CLK_REG (SUNXI_CCM_AON_BASE + E907_CLK_REG)
#define CCU_E90X_CLK_CPU_M_1 (0)
#define CCU_E90X_CLK_CPU_M_2 (1)

#define CCU_A27_CLK_REG (SUNXI_CCM_AON_BASE + A27L2_CLK_REG)
#define CCU_A27_CLK_CPU_M_1 (0)
#define CCU_A27_CLK_CPU_M_2 (1)
#define CCU_A27_CLK_CPU_M_3 (2)

#define CCU_HOSC_FREQ_DET_REG (SUNXI_CCM_AON_BASE + HOSC_FREQ_DET)
#define HOSC_24M_COUNTER (46875)
#define HOSC_40M_COUNTER (78125)
#define HOSC_FREQ_24M (24)
#define HOSC_FREQ_40M (40)

#define CCU_FUNC_CFG_REG (SUNXI_CCM_AON_BASE + PLL_FUNC_CFG_REG)

#define SUNXI_CCU_BASE (SUNXI_CCU_APP_BASE)
#define CCU_BASE (SUNXI_CCU_BASE)

#define CCU_GPADC_BGR_REG (GPADC_CLK_REG)
#define CCU_UART_BGR_REG (BUS_CLK_GATING0_REG)
#define CCU_UART_RST_REG (BUS_Reset0_REG)
#define CCU_SPI0_CLK_REG (SPI_CLK_REG)
#define CCU_SPI_BGR_REG (BUS_CLK_GATING0_REG)
#define CCU_BUS_CLK_GATING0_REG (BUS_CLK_GATING0_REG)
#define CCU_BUS_Reset0_REG (BUS_Reset0_REG)

#define CCU_SDMMC0_CLK_REG (SMHC_CTRL0_CLK_REG)
#define CCU_SDMMC1_CLK_REG (SMHC_CTRL1_CLK_REG)
#define CCU_SMHC0_BGR_REG_GATING (BUS_CLK_GATING1_REG)
#define CCU_SMHC0_BGR_REG_RESET (BUS_Reset1_REG)

#define SMHC0_BGR_REG_SMHC0_GATING_OFFSET (BUS_CLK_GATING1_REG_SMHC0_HCLK_EN_OFFSET)
#define SMHC0_BGR_REG_SMHC0_RST_OFFSET (BUS_Reset1_REG_HRESETN_SMHC0_SW_OFFSET)

#define TRNG_GATING_CLK_EN_OFFSET BUS_CLK_GATING0_REG_TRNG_PCLK_EN_OFFSET
#define TRNG_RESET_CLK_EN_OFFSET BUS_Reset0_REG_PRESETN_TRNG_SW_OFFSET

#define GATING_RESET_SHIFT (4)

#define SPI_CLK_PLL_PERI0 (307000000)
#define SPI_GATING_RESET_SHIFT (4)

/* E907 */
#define CCU_E907_CFG_RST (0x1 << 0)
#define CCU_E907_SYS_APB_RST (0x1 << 1)
#define CCU_E907_CFG_CLK_GATING (0x1 << 0)
#define CCU_E907_RSTN_REG (E907_RSTN_REG)
#define E907_CFG_BASE (0x43030000)
#define E907_STA_ADD_REG (E907_CFG_BASE + 0x0204)

/* a27l2 */
#define CCU_A27L2_MTCLK_REG (A27L2_MT_Clock_REG)
#define CCU_A27L2_MTCLK_EN (A27L2_MT_CLK_EN_CLOCK_IS_ON << REG_A27L2_MT_CLK_EN_OFFSET)
#define H_MTIME_REG (SUNXI_PLMT_BASE + 0x4)
#define L_MTIME_REG (SUNXI_PLMT_BASE)

//* SPIF clock bit field */
#define CCM_SPIF_CTRL_M(x) ((x) -1)
#define CCM_SPIF_CTRL_N(x) ((x) << 16)
#define CCM_SPIF_CTRL_HOSC (0x0 << 24)
#define CCM_SPIF_CTRL_PERI512M (0x1 << 24)
#define CCM_SPIF_CTRL_PERI384M (0x2 << 24)
#define CCM_SPIF_CTRL_PERI307M (0x3 << 24)
#define CCM_SPIF_CTRL_ENABLE (0x1 << 31)
#define GET_SPIF_CLK_SOURECS(x) (x == CCM_SPIF_CTRL_PERI512M ? 512000000 : 384000000)
#define CCM_SPIF_CTRL_PERI CCM_SPIF_CTRL_PERI384M
#define SPIF_GATING_RESET_SHIFT (5)

/* PLL MASK */
#define PLL_D_MASK (PLL_CPU_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK)
#define PLL_M_MASK (PLL_CPU_CTRL_REG_PLL_M_OFFSET)
#define PLL_N_MASK (PLL_CPU_CTRL_REG_PLL_N_CLEAR_MASK)
#define PLL_D_OFFSET (PLL_CPU_CTRL_REG_PLL_INPUT_DIV_CLEAR_MASK)
#define PLL_N_OFFSET (PLL_CPU_CTRL_REG_PLL_N_OFFSET)

#define PLL_OUTPUT_GATE_MASK (PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_CLEAR_MASK)
#define PLL_OUTPUT_GATE_Enable \
    (PLL_CPU_CTRL_REG_PLL_EN_ENABLE << PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET)
#define PLL_OUTPUT_GATE_Disable \
    (PLL_CPU_CTRL_REG_PLL_EN_ENABLE << PLL_CPU_CTRL_REG_PLL_OUTPUT_GATE_OFFSET)
#define PLL_EN_MASK (PLL_CPU_CTRL_REG_PLL_EN_CLEAR_MASK)
#define PLL_Enable \
    (PLL_CPU_CTRL_REG_PLL_EN_ENABLE << PLL_CPU_CTRL_REG_PLL_EN_OFFSET)
#define PLL_Disable \
    (PLL_CPU_CTRL_REG_PLL_EN_DISABLE << PLL_CPU_CTRL_REG_PLL_EN_OFFSET)
#define PLL_LDO_MASK (PLL_CPU_CTRL_REG_PLL_LDO_EN_CLEAR_MASK)
#define PLL_LDO_Enable                  \
    (PLL_CPU_CTRL_REG_PLL_LDO_EN_ENABLE \
     << PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET)
#define PLL_LDO_Disable                  \
    (PLL_CPU_CTRL_REG_PLL_LDO_EN_DISABLE \
     << PLL_CPU_CTRL_REG_PLL_LDO_EN_OFFSET)
#define PLL_LOCK_EN_MASK (PLL_CPU_CTRL_REG_LOCK_ENABLE_CLEAR_MASK)
#define PLL_LOCK_EN_Enable               \
    (PLL_CPU_CTRL_REG_LOCK_ENABLE_ENABLE \
     << PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET)
#define PLL_LOCK_EN_Disable               \
    (PLL_CPU_CTRL_REG_LOCK_ENABLE_DISABLE \
     << PLL_CPU_CTRL_REG_LOCK_ENABLE_OFFSET)
#define PLL_LOCK_MASK (PLL_CPU_CTRL_REG_LOCK_CLEAR_MASK)

#endif// __SUN20IW5_REG_CCU_H__
